Merge pull request #3082 from siliconcompiler/flist-reader

add support for flist import handling
siliconcompiler · Dec 20, 2024 · 4760d91 · 4760d91
2 parents dff0f14 + a352a58
commit 4760d91
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Showing 5 changed files with 148 additions and 1 deletion.
diff --git a/siliconcompiler/core.py b/siliconcompiler/core.py
@@ -1074,6 +1074,50 @@ def add(self, *args, field='value', step=None, index=None, package=None):
         except (ValueError, TypeError) as e:
             self.error(str(e))
 
+    def import_flist(chip, filename):
+        '''
+        Add input files, include directories, and defines from an flist
+
+        Args:
+            filename (path): Path to flist file
+        '''
+
+        if not os.path.isfile(filename):
+            raise FileNotFoundError(filename)
+
+        package_name = f'flist-{os.path.basename(filename)}'
+        package_dir = os.path.dirname(os.path.abspath(filename))
+
+        def __make_path(rel, path):
+            path = utils._resolve_env_vars(chip, path)
+            if os.path.isabs(path):
+                if path.startswith(rel):
+                    return os.path.relpath(path, rel), package_name
+                else:
+                    return path, None
+            return path, package_name
+
+        chip.register_source(
+            package_name,
+            path=package_dir)
+        with utils.sc_open(filename) as f:
+            for line in f:
+                line = line.strip()
+                if not line:
+                    continue
+                if line.startswith("//"):
+                    continue
+                if line.startswith("+incdir+"):
+                    line = line[8:]
+                    path, package = __make_path(package_dir, line)
+                    chip.add('option', 'idir', path, package=package)
+                elif line.startswith("+define+"):
+                    line = line[8:]
+                    chip.add('option', 'define', line)
+                else:
+                    path, package = __make_path(package_dir, line)
+                    chip.input(path, package=package)
+
     ###########################################################################
     def input(self, filename, fileset=None, filetype=None, iomap=None,
               step=None, index=None, package=None):

diff --git a/siliconcompiler/utils/__init__.py b/siliconcompiler/utils/__init__.py
@@ -333,7 +333,7 @@ def _resolve_env_vars(chip, filepath):
     # variables that don't exist in environment get ignored by `expandvars`,
     # but we can do our own error checking to ensure this doesn't result in
     # silent bugs
-    envvars = re.findall(r'\$(\w+)', resolved_path)
+    envvars = re.findall(r'\$\{?(\w+)\}?', resolved_path)
     for var in envvars:
         chip.logger.warning(f'Variable {var} in {filepath} not defined in environment')
 

diff --git a/tests/core/data/flist/dummy.v b/tests/core/data/flist/dummy.v
diff --git a/tests/core/data/flist/files.flist b/tests/core/data/flist/files.flist
@@ -0,0 +1,5 @@
+// Dummy files
+
+dummy.v
++incdir+.
++define+TEST=1
diff --git a/tests/core/test_flist.py b/tests/core/test_flist.py
@@ -0,0 +1,98 @@
+import os
+import pytest
+
+from siliconcompiler import Chip
+
+
+@pytest.mark.nostrict
+def test_import_flist_rel_paths(datadir):
+    chip = Chip('dummy')
+    chip.import_flist(os.path.join(datadir, 'flist', 'files.flist'))
+
+    assert "flist-files.flist" in chip.getkeys('package', 'source')
+
+    assert chip.get('input', 'rtl', 'verilog') == ["dummy.v"]
+    assert chip.get('input', 'rtl', 'verilog', field='package') == ['flist-files.flist']
+    assert None not in chip.find_files('input', 'rtl', 'verilog')
+
+    assert chip.get('option', 'idir') == ["."]
+    assert chip.get('option', 'idir', field='package') == ['flist-files.flist']
+
+    assert chip.get('option', 'define') == ["TEST=1"]
+
+
+@pytest.mark.nostrict
+def test_import_flist_abs_paths():
+    chip = Chip('dummy')
+
+    dummy_path = os.path.abspath('dummy.v')
+    with open(dummy_path, 'w') as f:
+        f.write("// test\n")
+
+    os.makedirs("flist", exist_ok=True)
+    os.makedirs("incs", exist_ok=True)
+
+    with open('flist/flist', 'w') as f:
+        f.write("// test\n")
+        f.write(dummy_path + "\n")
+        f.write("+incdir+" + os.path.abspath("incs") + "\n")
+
+    chip.import_flist('flist/flist')
+
+    assert "flist-flist" in chip.getkeys('package', 'source')
+
+    assert chip.get('input', 'rtl', 'verilog') == [os.path.abspath("dummy.v")]
+    assert chip.get('input', 'rtl', 'verilog', field='package') == [None]
+    assert None not in chip.find_files('input', 'rtl', 'verilog')
+
+    assert chip.get('option', 'idir') == [os.path.abspath("incs")]
+    assert chip.get('option', 'idir', field='package') == [None]
+
+
+@pytest.mark.nostrict
+def test_import_flist_abs_package_paths():
+    chip = Chip('dummy')
+
+    dummy_path = os.path.abspath('dummy.v')
+    with open(dummy_path, 'w') as f:
+        f.write("// test\n")
+
+    os.makedirs("incs", exist_ok=True)
+
+    with open('flist', 'w') as f:
+        f.write("// test\n")
+        f.write(dummy_path + "\n")
+        f.write("+incdir+" + os.path.abspath("incs") + "\n")
+
+    chip.import_flist('flist')
+
+    assert "flist-flist" in chip.getkeys('package', 'source')
+
+    assert chip.get('input', 'rtl', 'verilog') == ["dummy.v"]
+    assert chip.get('input', 'rtl', 'verilog', field='package') == ['flist-flist']
+    assert None not in chip.find_files('input', 'rtl', 'verilog')
+
+    assert chip.get('option', 'idir') == ["incs"]
+    assert chip.get('option', 'idir', field='package') == ['flist-flist']
+
+
+@pytest.mark.nostrict
+def test_import_flist_env_paths():
+    chip = Chip('dummy')
+
+    dummy_path = os.path.abspath('dummy.v')
+    with open(dummy_path, 'w') as f:
+        f.write("// test\n")
+
+    with open('flist', 'w') as f:
+        f.write("// test\n")
+        f.write("${SRC_PATH}/dummy.v\n")
+
+    chip.set('option', 'env', 'SRC_PATH', os.path.dirname(dummy_path))
+    chip.import_flist('flist')
+
+    assert "flist-flist" in chip.getkeys('package', 'source')
+
+    assert chip.get('input', 'rtl', 'verilog') == ["dummy.v"]
+    assert chip.get('input', 'rtl', 'verilog', field='package') == ['flist-flist']
+    assert None not in chip.find_files('input', 'rtl', 'verilog')