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This repository is a design and implementation of the IIT-B RISC ISA

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Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
Multicycle IITB_RISC		Multicycle IITB_RISC
Pipeline-IITB_RISC		Pipeline-IITB_RISC
README.md		README.md

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RISC-Processor-design

Team Members

Shubhang Bhatnagar
Aniket Bhatia
Chinmay Gurjarpadhye
Vineet Kotariya

Project

This project is a design and implementation of a RISC processor based on the IITB-RISC ISA (Instruction Set Architecture) . It contains-

Multicycle RISC processor
Pipelined RISC processor

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This repository is a design and implementation of the IIT-B RISC ISA

risc-processor iitb-risc

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VHDL 99.4%
Other 0.6%