TEMPORARY FORK of the riscv-compliance repository

RISC-V Configuration Validator

Advanced Architecture Labs with CVA6

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

RISC-V Formal Verification Framework

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

The MiBench testsuite, extended for use in general embedded environments

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

PLIC Specification

The main Embench repository

The Scale4Edge ecosystem VP

Brief SystemC getting started tutorial

RISC-V SystemC-TLM simulator

RISC-V Opcodes

Repo for CHERI development system

cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.

HW Design Collateral for Caliptra RoT IP

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

UVM 1.2 port to Python

The FreeBSD src tree publish-only repository. Experimenting with 'simple' pull requests....

Documentation developer guide

Intel Homomorphic Encryption Acceleration Library for FPGAs, including open source implementation of FPGA kernels for accelerating NTT, INTT, Keyswitch and Dyadic Multiplication modular arithmetic …

synthesiseable ieee 754 floating point library in verilog

Instruction Set Generator initially contributed by Futurewei

A complete computer science study plan to become a software engineer.

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems