This site contains extensive information about the control boards used in some 1980s hard drives made by Seagate.

Full schematics and even KiCad layouts are available for a number of different boards. My hope is that this will

1. Aid anyone attempting to repair one of these drives. Loading the schematic and layout in KiCad will let you click on a part on the layout and highlight it in schematic.
2. Inform anyone studying the history of small hard drives. For example, this information shows how Seagate integrated various functions into custom chips.

Below is a table linking specific drive models with the part numbers of their matching control boards.

The control boards are typically held to the drive by three screws. Two of the screws are insulated from the PCB ground with plastic washers, but one of them makes a solid ground connection to the chassis. This is (as far as I can tell) always the screw closest to the power connector.

Early ST-225 boards have an 18-pin header going to the read/write heads, but the flex cable has a 16-pin connector. It should be plugged in offset to the pin 1 end of the header, allowing pins 17 and 18 on the header to hang outside the connector.

For a stepper-motor hard drive, the motor phase is rather important because the rotor will "clock" to the phase you drive it with. The firmware uses this while searching for the index tracks so it can jump 8 tracks at a time, since it knows the inner index track is aligned to phase 5 and the outer to phase 7.

The "Track" column indicates the track as visible to the user (the controller card in the PC). From this layout, you can see that the data area contains 615 total tracks. The landing zone is specified at track 670 which is safely outside the data area and away from the inner index marker track.

The "Firmware Track" column is offset by 2 because this is how the drive's firmware numbers them; it limits the MFM controller from track 2 to track 672. This implies that there is no protection against the controller overwriting the inner index track -- you must enter the drive parameters in the BIOS correctly! The outer index track is inaccessible during normal operation.

Note: Motor phase count is 0-7 since the motor is half-stepped.

The index marker track contains the following repeating information:

When the MCU PA7 is set as an input (logic 1), the drive will hold the hall-effect signal divider in reset as long as the 1.75MHz marker signal is present.

The index marker tracks are present only on head 0; none of the other surfaces contain this information.

This drive has firmware and bad sector information recorded on tracks -1 and -2, presumably multiple copies located on each surface.

More information to come at a later date.

Index marker track:

This ST-225 control board integrates the functions of both circuit boards in the ST-412/419 generation. Some functions have been integrated in LSI chips.

The PCB schematic and layout for 20301 are available, see st225/20301.

The PCB schematic and layout for 20527 are available, see st225/20527.

There are several variations of the 20301 board:

• 1986 example: 74273, 2716, RP6 are not stuffed.

• 1987 example: 74273, 2716, RP5, RP6, RP7, RP8, RP9, RP10, C18, C31, CR4, 7445(8C, 8B) are not stuffed. Q9 is replaced with a 620 ohm resistor between the emitter and base terminals. This disables the fancy pulldown resistors on the stepper motor circuit (probably a cost reduction).

Unlike the EPROM chip on the ST-251 boards, the 2716 chip seems to be used to store tables for controlling the stepper motor.

20301 to 20527 changes

• A better LC power filter has been added to the 12V and 5V power inputs.
• The two 7445 chips driving the stepper motor have been depopulated and all but one resistor array have been removed. Presumably a cost reduction.
• The circuit driving the stepper motor chip's SET pin has been depopulated and jumpered with a resistor, probably a cost reduction.
• The footprint for the 2716 EPROM and the 74273 latch (to support external firmware) have been removed completely.
• The transistor driving the START#/RUN connection to the spindle driver has been swapped with a spare 7406.
• Several discrete resistors in the spindle driver circuit have been incorporated into resistor arrays, including a fully custom array, the 12497-001 which contains a 3.3K, 470, 560, and 2.2K resistor.
• The reference clock circuit driving the spindle motor control IC has changed, presumably to put less of a load on the 2MHz MCU crystal.
• The transistor array and resistor arrays used to drive the read/write head center tap connections (as well as the two write current driver transistors) have been consolidated into LSI 10014-002.
• Read/write channel SSI280 has been expanded and modified (now called 10206-002) with 3 additional one-shot timers in the pulse detector circuit as well as a more complex 2-part final differential signal filter. Compare this new design to the later ST-251.
• New one-shot devices have been added to the MCU's read channel. This read channel allows the MCU to detect the index and guard band tracks recorded at manufacture time. Presumably these changes make the MCU's detection algorithms more tolerant of defects on these tracks. It is not known if drives with these boards have a different pattern recorded on the index and guard band tracks.
• The reset signal pulse, derived from the DC_UNSAFE# signal comparators in the 10206-002, has been shortened significantly.
• The hall sensor signal to the MCU is generated with a real one-shot chip instead of two chained flip flops with RC filters.

A note about 20527 to ST-251 boards, like the 20629

There appears to be a clear evolution between the 20527 ST-225 board and the early ST-251 board, the 20629.

• The read channel is nearly identical, with the preamp and first stage filter being exactly the same. The second stage filter has been adjusted and the one-shots are different.
• Support for two additional read/write heads has been added.
• The spindle motor is now a three-phase BLDC (instead of 2-phase) with three hall effect sensors (instead of one). A single chip 3-phase motor driver has been bolted onto the existing speed control chip.
• The stepper motor is now a really wild 5-phase custom design with a slew of new control chips, including a ring detector LSI that is used to optimize the motor voltage, and an auto-retract chip that takes care of parking the heads during a power-down. All this design effort almost halves the average seek time.
• A new LSI incorporates the MCU read channel one-shot devices along with a bunch of discrete buffers.
• The MCU's external ROM chip is back. Presumably this was used extensively for internal firmware development and left in the shipping product until mask ROM MCUs became available.

The PCB schematic and layout for 20427 are available, see st225n/20427. This board is used in the ST-225N.

This board has a read/write channel similar to the plain ST-225, but the rest of it is quite different. All of the chips are now surface mount, including the Seagate custom devices.

The stepper motor driver has been replaced with a simple off-the-shelf MC3479.

An on-board data separator (DP8455) has been added, along with an Adaptec chipset for SCSI:

• AIC-250L - MFM encoder/decoder
• AIC-010L - Programmable mass storage controller
• AIC-300 - Dual port buffer controller

The 6500/1 microcontroller has been replaced with an 8051. The 8051 has much more intelligence than the old design which only implemented seek buffering and the index track search. The firmware hasn't been completely analyzed yet but it

• Programs and manages the Adaptec chipset to implement the SCSI interface
• Handles the stepper motor seek
• Loads extra firmware into its dedicated SRAM chip from "hidden" tracks on the drive surface

Some of the custom chips seem to share functionality with the ST-251, which may have been under development at the same time.

• The 11647-501 was used on the ST-251 as the MFM interface, but on this board it performs housekeeping functions and is wired differently.
• The 11695-502 has been repackaged into SMD (unlike the older 11695-002) and was also used on the ST-251 to control the spindle driver.

Unlike the earlier ST-225 and ST-412 generations, drives with this board use 5-phase steppers and can seek nearly twice as fast as the ST-412. A lot of discrete logic and analog circuitry has been integrated into several LSI chips.

The PCB schematic and layout for 20629 are available, see st251/20629. This board is used in the ST-251 (plain).

The PCB schematic and layout for 20938 are available, see st251/20938. This board is used in the ST-251-1 as well as the ST-277R (-300 version).

The PCB schematic and layout for 21020 are available, see st251/21020. This board is used in the ST-277R-1.

20629 to 20938 changes

Changes to the stepper motor circuits:

• The L293 bridge chips have been replaced with custom drivers (11721-501).
• Another custom chip, the 11743-501, has been added to control the enable state of each stepper phase.
• The DC_UNSAFE# signal has been split and no longer controls the stepper motor enable. A new RETRACT# signal, generated by the 10223-502 chip's power good monitoring comparators, does this instead. (DC_UNSAFE# is generated by power good comparators in the 10206-501 read/write circuit.)
• The stepper sequencer output enable (pin 3) is now driven by the RETRACT# signal instead of being pulled up.
• The stepper sequencer has been moved from the regular 5V rail to the spindown keepalive rail (+5VP).
• The stepper driver chips now get 5V from the regular 5V rail instead of a filtered rail (+5F).
• The ring detector LSI has had a jumper installed in series with the reset input (not populated by default)
• 1K series resistors have been added between the stepper windings and the ring detector LSI.
• The digitally-controlled stepper motor voltage rail now has more bulk capacitance (C63, with series resistor for stability).

Changes affecting the spindle motor drive circuit:

• The spindle motor driver, the speed control LSI (11692-502) and the index comparator LM339 have been combined in a single custom spindle driver IC, the 11791.
• The braking bridge rectifier (UC3610) has been removed and two additional MOSFETs have been added for braking.

Changes affecting the read/write circuit:

• The read/write head center tap driver filter now gets power from the regular 5V rail instead of sharing it with the stepper driver chips.
• Write termination resistor R21 has been moved to be near 11E (the receive side) for signal integrity.

Some changes imply changes to the drive firmware. This means that firmware meant for the previous revision will no longer work on this board:

• The MCU has been swapped with a mask ROM chip (80118-502) and the EPROM and address latch (6B) are no longer populated
• The MCU port PA7 is now tied through a resistor (R33) to ground. It no longer drives the stepper motor ALL_PHASES_ON signal. Presumably newer firmware can check for this strapping resistor to detect which board revision it's running on.
• The ALL_PHASES_ON signal is now driven by bit 7 of the external IO port (the 'LS273).
• The INDEX_SYNC# signal to sync up the hall state machine is now triggered by the output port 'LS273 bit 0 instead of being triggered by a write to 0x0105.
• A write to 0x0105 now pulses the stepper sequencer 7C RESET# pin (14), instead of it being controlled by bit 0 of the output port 'LS273.
• The MCU port PB4 no longer goes to the debug test points. Instead, it's been routed (along with PB5 and PB6) to the new 11743-501 stepper phase control chip inputs S1, S2, and S3.

20938 to 21020 changes

The electrical changes here are fairly minor. The layout has some moderate changes to improve routing and add the (few) new parts.

• The spindle motor driver IC is now the 11738-002 which has a slightly different package.
• The spindle motor IC's reference resistor now has two possible values, set by a transistor driven by a toggle flip flop (1F section A) by writing to address 0x0106. The default is 13K (19.6K || 38.3K) and, when toggled, it is just 38.3K. Presumably this is for power savings during operation by running the spindle motor at a reduced current.
• The MCU has a new part number, 80118-505. Presumably this is new firmware that knows how to reduce the spindle driver power.
• The MCU's clock crystal is now just a single through-hole footprint instead of a dual SMT/PTH one.
• The steering diode IC is now the 10189-502 (not the 10189-521).
• The H-bridge enable controller is now the 11468 instead of the 11743-501.

The firmware from the 20629 board has been dumped. The label is marked "ST 251 / LSIL18". The firmware has been fed through Ghidra and a good chunk of it has been commented and labeled. See the repository. Some parts of it are not understood.

The firmware from the ST-225's ROM microcontroller, 80007-001, has been dumped, disassembled, and commented. See st225/firmware.

Fun facts:

• Some (but not all) ST-225 logic boards have an array of resistors and two 7445 chips. These are connected to the stepper motor and are used to adjust the voltage on individual windings to subtly shift the position of the stepper motor (microstepping). This is used in recovery mode.
• Early ST-225 logic boards have a latch and EPROM chip. These are not populated. They are not used to store firmware. The microcontroller's internal ROM contains code that uses this external EPROM as a lookup table of 1 byte per track. Each contains two 4-bit values used to microstep the head position (two values because the value can be different if you are stepping inwards to the track or stepping outwards to the track). This may have been used to provide a custom "defect map" for a single-platter drive, using the stepper to avoid bad areas on the platter.
• An undocumented "pause mode" appears in the firmware. By pulling PA4 low (pin 34 of the MCU), it enters a state where it allows all GPIO pins to go high/float. Presumable this was useful for debugging.

TBD, stay tuned.

This device interfaces with the MFM control cable. In the ST-225N, a similar device provides glue logic but seems to be used in a different operating mode.

Pin Description

Functional Description

Several signals are simply buffered to the MFM bus and active only when the drive select line is valid:

• DRV_SEL_OUT#
• READY_OUT#
• TRK0_OUT#
• WRT_FAULT_OUT#
• INDEX_OUT#
• SEEK_COMPLETE#

Other signals are returned from the MFM bus only when the drive select line is valid:

• STEP#
• DIR#

The INDEX_OUT# signal is passed through a one-shot timer run off the HALL input divided by two. On every other HALL pulse, it goes low for about 1213 cycles of the CLK input. This is about 600us. The INDEX_SYNC# signal, when held low, prevents the INDEX_OUT# signal from asserting. On the rising edge of INDEX_SYNC#, the HALL input divider is resynchronized and the first pulse on HALL will generate an index output pulse. The second pulse is skipped, but the third makes it through, and so forth.

The WRT_FAULT_OUT# is the WRT_FAULT# input but delayed by 6 clock cycles.

The stepper direction signal going into the MCU is a latched version of the one present on the MFM bus, latched when STEP is pulsed.

There is an SR latch driving the SEEK_COMPLETE# signal. This signal deasserts when STEP# asserts, RESET# asserts, or DC_UNSAFE# asserts. It asserts when the MCU_SEEK_DONE# signal asserts.

The INDEX_TRACK# signal is somewhat complex. The internal circuit isn't well understood but it looks at the data coming from the read channel and detects a special signal recorded on track -2. This is "2F" or 00101111 which occurs, repeating for 4ms, at the index location. The rest of the track contains a 1.75MHz signal which does not trigger this pin. For CLK=2MHz, this pin seems to go low when READ_DATA falls between 1.958MHz and 2.038MHz.

The INDEX_TRACK# signal seems to depend on internal counters. If READ_DATA pulses at least once per CLK high/low, in 9 READ_DATA pulses, then INDEX_TRACK# asserts low on the 9th READ_DATA rising edge. This triggers another one-shot device that ensures that INDEX_TRACK# continues to be asserted for 5 rising CLK edges after READ_DATA stops pulsing. DC_UNSAFE# resets both the READ_DATA pulse detector and the INDEX_TRACK# one-shot.

These devices drive the center tap connections of the R/W heads, and also provides two outputs to drive the write current resistor divider.

The 10188-501 comes in an SOIC package while the 10014-002 comes in a DIP package.

Pin Description

Functional Description

The center tap driver chip drives the center tap of each head coil depending on the head select input state. During a write fault (WRT_FAULT_IN = 1) all heads are deselected.

(VCTAP in the table is actually VCTAP - 0.25V.)

Unselected heads are driven to VHS * 0.86. There may be an internal voltage divider but this is buffered with a low (0.3 ohm) impedance driver before being switched onto the head output.

VHS (Voltage Head Safe) uses a resistor network to aggregate the voltages on all the head center tap connections. The adjacent read/write channel LSI monitors this voltage with comparators. If the voltage is too high, that indicates that multiple heads have been selected for writing, which triggers a write fault. A voltage that is too low indicates that no heads are selected for writing, which also triggers a write fault.

The chip also includes a very simple two-transistor driver for the write current selection. This is used for up to 4-zone recording.

When RIWR1 is driven high, IWR1 is driven to +12V. Otherwise, IWR1 floats. When RIWR2 is driven high, IWR2 is driven to +12V. Otherwise, IWR2 floats.

This is the head select steering matrix and read preamplifier.

The 10189-521 comes in an SOIC package while the 11642-001 comes in a DIP package.

Pin Description

Functional Description

The currently selected read/write head has the common (center tap) winding brought to a voltage higher than the center tap windings of all the other heads. This forward biases internal steering diodes, while reverse biasing the internal diodes connected to deselected heads.

A differential signal placed on the DI inputs appears on the connection of the currently selected head. This is used to write track data. Leave the inputs high to avoid writing data--an output only sinks current when a DI input sinks current.

Differential signals from the currently selected read/write head gets amplified by the internal read preamp and driven out to the DO outputs. A gain network (R, C, or RLC) can be attached to the two GAIN pins. Lower impedances increase the gain, as shown approximately in this table.

The preamp is similar to the NE592 video amplifier chip. See the datasheet for examples of different gain networks. Typically a capacitor is used here to create a differentiator (high pass) function. This aids the peak detection function in the read channel (see the next section.)

This device incorporates the read channel and the write amplifier circuitry.

Pin Description

The functionality of this device is similar to the 10206-501 but with a simpler pulse generation section including a single one-shot.

These devices incorporate both the read channel and the write amplifier circuitry.

The 10206-501 comes in the 44-pin PLCC package while the 10206-002 comes in the 40-pin DIP package.

Pin Description

Detailed Description

The write drive circuit takes differential digital data from the WDATA_IN pins and outputs it (with a current set by the WRITE_CUR pin) on the WDO pins during write mode. Write mode is entered when DC_UNSAFE# is deasserted, WRT_OK is asserted, and WRT_GATE# is asserted (DRV_SEL# is ignored).

Voltage Head Safe (VHS) senses when the average center tap voltage of the heads exceeds a limit of about 3.5V, and when this happens, WRT_FAULT# asserts, because this indicates that multiple heads have been selected. If the voltage is below some minimum threshold (indicated that no heads are selected) it may also trigger a write fault.

VCTAP is driven to 12V in write mode and otherwise goes to 5.3V (for reads). It is controlled by WRT_GATE# alone, for some reason. This drives the center tap voltage of the currently-selected head.

The power supply monitor asserts DC_UNSAFE# when the 5V rail falls below 4.2V (rising threshold is 4.23) or when the 12V rail falls below 9.54V (rising threshold is 9.67V).

The preamp section is very similar to the NE592. A RLC network is typically connected across the gain terminals to provide a bandpass filter characteristic. This shapes the differentiated signal coming from the head preamp (located in the head matrix IC).

Typically the circuit on the drive logic board splits this diffential output signal into two sets of signals with different filters applied. Each set of signals has a differential comparator input that each drives a one-shot timer.

Comparator C1 drives one-shot TMG1. Comparator C2 drives one-shot TMG2, and TMG2 drives TMG3. In order to generate an output pulse, the logic is not well understood but it seems that comparator C1 must trigger after comparator C2 (due to an external phase shift network).

If the conditions are met to generate an output pulse, the fourth one-shot trigger, TMG4, triggers for its fixed pulse width time.

Each one-shot pin works in stages:

1. The pin is pulled up to (mostly) 5V. This discharges the timing capacitor tied between the pin and 5V.
2. The pin is released and allowed to discharge through the external pulldown resistor to 90% of 5V. This triggers the output of the one-shot. By using the narrow threshold (only 10% of the total RC curve) the timing result is approximately linear.
3. Some pins discharge the timing capacitor again to 5V, others hover at the 90% of 5V mark.

The timing value can be approximated as T = 0.1 * R * C.

In the scope shot above, all the pins have had 10K resistors installed and the following capacitor values

• Pin 32: 270pF
• Pin 33: 470pF
• Pin 34: 680pF
• Pin 35: 2200pF

These are much larger than the usual values used by the hard drive, which is typically 47pF, to make the scope shot easier to interpret.

Typical values (on the ST-251) are:

• TMG1: 82ns - comparator C1
• TMG2: 47ns
• TMG3: 69ns - total time for comparator C2 is 116ns
• TMG4: 42ns - output data pulse width

This device is used to drive 4-phase stepper motors.

Pin Description

Functional Description

This IC includes build-in power driver transistors as well as a step table and counter for 4-phase stepper motors.

Std: Standard step mode (1/2STEP=0, MODE=x, DIR=0)

Half: Half step mode (1/2STEP=1, MODE=0, DIR=0)

AltHalf: Alternate half step mode (1/2STEP=1, MODE=1, DIR=0)

When DIR = 1, the phase is decremented and goes in reverse order (right to left) on the table.

(Z means the phase is floating, not driven high or low.)

The SET pin must be connected with a resistor (around 50K) to ground to bias up the chip. If it is pulled high or left floating, then the chip will not drive any of the outputs and the internal phase counter will be reset to phase 0.

The step sequencer generates the 5-phase signals that drive the stepper motor power driver chips.

Pin Description

Detailed Description

This device is basically a sequence controller chip that drives the phase signals going to the stepper motor driver chips.

They follow these phase tables.

For each phase, the states below correspond with the following output states. Phase 0 corresponds with the phase after a reset. When DIRECTION=0, proceed from phase 0, 1, 2...9 and wrap back to 0. When DIRECTION=1, proceed from phase 0, 9, 8, 7...1.

Std: Standard step mode (HALFSTEP#=1, HALFSTEP2#=x, DIRECTION=0)

Half: Half step mode (HALFSTEP#=0, HALFSTEP2#=1, DIRECTION=0)

AltHalf: Alternate half step mode (HALFSTEP#=0, HALFSTEP2#=0, DIRECTION=0)

This device controls the H-bridge enable lines for each phase of the stepper motor.

Pin Description

Detailed Description

The power driver chips for the stepper motor phase windings are typically L293 or similar totem-pole devices. That means that each phase connection can be driven high or low depending on the input state, but the output driver can also be disabled so it pulls neither high nor low. However, the step sequencer chip, 11782-501, can only drive both phase outputs (+ and -) low to indicate that the driver should be disabled. If both coil drivers are driven low, the coil is effectively short-circuited and will brake the motor, so this chip detects that and disables both coil drivers.

If the ALLON line is low, then each phase output enable EN_x will track the corresponding + and - inputs by XORing them together. So if both inputs are low or both are high, then the phase output enable will go low. If one input is high and the other is low, then the phase output enable goes high.

If the ALLON line is high, then all phase output enables go high regardless of the motor phase inputs.

The output mask select mux inputs, S1, S2, and S3, can selectively force individual phase output enables low according to this table:

Empty boxes follow the state prescribed by the ALLON line and the +/- motor phase inputs.

Typical firmware leaves all three select mux inputs low, but one section brings S1 high, possible for stepper motor voltage calibration.

This device moves the heads to the landing zone when it detects a power loss.

Pin Description

Functional Description

This device monitors the 5V and 12V input pins. When either pin falls below their respective undervoltage thresholds, this begins retraction mode. The retract pin asserts low and the motor winding drivers activate, driving either high, low, or high impedance depending on the 5-phase step table. The step speed is controlled by the clock input, typically tied to one of the coils on the spindle motor. The input has a 2-level comparator, requiring a signal amplitude that falls below 2.5V and rises above 3.6V.

When retraction mode is entered, the CT pin gets driven with a 10uA current source so the capacitor begins to charge. Once it reaches 2.44V, the MOSFET brake driver pin goes from the low state to the high impedance state. External pullup circuitry then drives the brake MOSFETs to stop the spindle motion.

Calculate the delay time as T = C * 2.44V/10e-6. Using a 6.8uF capacitor, the delay time is about 1.66s. This is the amount of time given to allow the stepper motor to retract the heads up against the hard stop before the spindle brake is activated.

The step sequence is as follows:

This is designed for a 5-phase stepper motor (10 wire) but it does not drive phases B and C.

This device serves two purposes:

• Provided a digitally-controlled linear regulated power source to the stepper motor
• Detect back-EMF "ringing" cycles on the stepper motor windings

Pin Description

Functional Description

The device has a linear regulator with a 7-bit DAC controlling the voltage. The topology is simple. The output voltage is monitored by an external resistor divider tied to FB and compared directly with the VREF input. The error amplifier output connects to the COMP pin for external compensation purposes. The DRV pin is inverted and connects to an external PNP pass transistor (or an arrangement of an NPN and a PNP).

Communications to the device occurs over a simple 8-bit SPI bus (no data output). Deassert the active-low CS# line and clock data, LSB first, into the device (CLK normally high, rising edge triggered), then release CS#. The data format is as follows:

The built-in DAC is a 7-bit device that drives a voltage from 0 to VREF/2 onto the DAC_SET pin. An external resistor connected to ground turns this into a current that is drawn from the FB pin. The higher this current, the more the output voltage increases.

The nominal output voltage is Vref * (1 + Rtop/Rbot). With the values in the ST-251 schematic, this is 3.75V, assuming the DAC is set to 0.

The DAC increases the output voltage by Rtop * (VDAC / RDAC_SET). VDAC is just (n/127) * (VREF/2). For example, a DAC code of 0x2A results in a DAC output voltage of 0.413V. Using the values in the ST-251 schematic, this is a current of 255uA pulled from the FB node. With an upper resistor of 10K, this corresponds with a voltage increase of 2.55V. The total output voltage is then 6.3V.

The ring detector is a window comparator that examines one of five possible differential inputs, A-E. The input is selected using the SPI bus with the MSB set to 1 and the value 0-4 loaded into the LSBs.

The window threshold is controlled by the voltage applied to the RING_SET pin. It seems to be a percentage of that voltage. The output of the window comparator goes to a digitally-timed counter state machine which is incompletely understood but clocked by the SYS_CLK input. The output of this is passed along to the RING_DET output (which must be pulled up externally). In typical operation, this pin toggles on every edge of the ringing signal generated by the back EMF of the stepper motor winding.

This custom LSI chip controls and regulates the speed of the spindle motor. It seems to be nearly identical to the SSI 32M5901.

Pin Description

Function Description

This device generates commutated coil output control signals based on the hall effect sensor input. It regulates the speed by measuring the hall effect input against the 2MHz input reference clock frequency. The device assumes that there are two hall pulses per revolution and that the motor is to be regulated to 3600 RPM, or 120 hall pulses per second.

The device also monitors the number of reference clock pulses, and if hall effect pulses aren't received for a certain number of cycles, both COILA and COILB outputs are disabled (locked rotor protection).

The sense input is externally tied to a current sense resistor in series with the ground path of the driver transistors. The chip cuts off the COILA/COILB signal early when the current reaches a set limit.

When the 12V power supply falls below a threshold, the motor coil back EMF causes the COILA and COILB inputs to turn on simultaneously, braking the motor.

A large amount of Seagate drive information can be found on Bitsavers.

Some operational clues for the ST-225 are available in the ST-225 OEM Manual.

This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License. See https://creativecommons.org/licenses/by-sa/4.0/.