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RISC-V

The Open-Standard Instruction Set Architecture
README.md

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  1. riscv-isa-manual riscv-isa-manual Public

    RISC-V Instruction Set Manual

    TeX 3.7k 639

  2. docs-dev-guide docs-dev-guide Public

    Documentation developer guide

    TeX 86 30

  3. docs-spec-template docs-spec-template Public template

    Makefile 18 19

  4. docs-resources docs-resources Public

    24 14

Repositories

Showing 10 of 58 repositories
  • riscv-smmtt Public

    This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.

    riscv/riscv-smmtt’s past year of commit activity
    Makefile 35 CC-BY-4.0 15 1 4 Updated Oct 28, 2024
  • riscv-docs-base-container-image Public

    A base container image populated with the dependencies to build the RISC-V Documentation.

    riscv/riscv-docs-base-container-image’s past year of commit activity
    9 Apache-2.0 7 0 3 Updated Oct 28, 2024
  • riscv-opcodes Public

    RISC-V Opcodes

    riscv/riscv-opcodes’s past year of commit activity
    Python 690 BSD-3-Clause 300 23 25 Updated Oct 27, 2024
  • meta-riscv Public

    OpenEmbedded/Yocto layer for RISC-V Architecture

    riscv/meta-riscv’s past year of commit activity
    BitBake 364 139 17 (1 issue needs help) 0 Updated Oct 25, 2024
  • riscv-performance-events Public

    RISC-V Performance Events Specification

    riscv/riscv-performance-events’s past year of commit activity
    Python 4 CC-BY-4.0 2 5 0 Updated Oct 25, 2024
  • sail-riscv Public

    Sail RISC-V model

    riscv/sail-riscv’s past year of commit activity
    Coq 452 164 92 (1 issue needs help) 66 Updated Oct 25, 2024
  • riscv-control-transfer-records Public

    This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.

    riscv/riscv-control-transfer-records’s past year of commit activity
    Makefile 17 CC-BY-4.0 4 0 0 Updated Oct 24, 2024
  • riscv-cheri Public

    This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

    riscv/riscv-cheri’s past year of commit activity
    Python 50 CC-BY-4.0 29 36 (2 issues need help) 7 Updated Oct 23, 2024
  • riscv-isa-manual Public

    RISC-V Instruction Set Manual

    riscv/riscv-isa-manual’s past year of commit activity
    TeX 3,665 CC-BY-4.0 639 190 (2 issues need help) 16 Updated Oct 22, 2024
  • learn Public

    Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

    riscv/learn’s past year of commit activity
    531 62 0 2 Updated Oct 19, 2024
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