Create crate edatool for lvs, drc, pex, simulation interfaces (#46)

* Create crate edatool for lvs, drc, pex, simulation interfaces * update pointers to magic_pex and netgen_lvs
rahulk29 · Mar 18, 2022 · 994b922 · 994b922
1 parent 3cc7210
commit 994b922
Show file tree

Hide file tree

Showing 25 changed files with 124 additions and 52 deletions.
diff --git a/.gitmodules b/.gitmodules
@@ -1,6 +1,6 @@
 [submodule "sram22/src/verification/plugins/netgen_lvs"]
-	path = sram22/src/verification/plugins/netgen_lvs
+	path = edatool/src/plugins/netgen_lvs
 	url = git@github.com:rahulk29/netgen_lvs.git
 [submodule "sram22/src/verification/plugins/magic_pex"]
-	path = sram22/src/verification/plugins/magic_pex
+	path = edatool/src/plugins/magic_pex
 	url = git@github.com:rahulk29/magic_pex.git
diff --git a/Cargo.lock b/Cargo.lock
diff --git a/Cargo.toml b/Cargo.toml
@@ -1,6 +1,7 @@
 [workspace]
 
 members = [
+  "edatool",
   "fanout",
   "magic_vlsi",
   "micro_hdl",

diff --git a/edatool/Cargo.toml b/edatool/Cargo.toml
@@ -0,0 +1,37 @@
+[package]
+name = "edatool"
+version = "0.1.0"
+edition = "2021"
+authors = ["Rahul Kumar <rahulkumar@berkeley.edu>"]
+description = "Rust interfaces to EDA tools for circuit design"
+
+# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+
+[dependencies]
+thiserror = "1.0"
+magic_vlsi = { path = "../magic_vlsi" }
+serde = { version = "1.0", features = ["derive"] }
+serde_json = "1.0"
+log = "0.4"
+handlebars = "4.2"
+portpicker = "0.1"
+prost = "0.9"
+bytes = "1.1"
+
+[build-dependencies]
+prost-build = "0.9"
+
+[dev-dependencies]
+tempfile = "3.3"
+approx = "0.5"
+
+[features]
+default = ["open_source"]
+netgen_lvs = []
+magic_drc = []
+magic_pex = []
+calibre_lvs = []
+calibre_drc = []
+ngspice_sim = []
+open_source = ["netgen_lvs", "magic_drc", "magic_pex", "ngspice_sim"]
+mentor = ["calibre_lvs", "calibre_drc"]
diff --git a/edatool/src/error/mod.rs b/edatool/src/error/mod.rs
@@ -0,0 +1,27 @@
+use thiserror::Error;
+
+#[derive(Debug, Error)]
+pub enum EdaToolError {
+    #[error("io error: {0}")]
+    Io(#[from] std::io::Error),
+
+    #[error("magic error: {0}")]
+    Magic(#[from] magic_vlsi::error::MagicError),
+
+    #[error("invalid template: {0}")]
+    Template(#[from] handlebars::TemplateError),
+
+    #[error("error rendering template: {0}")]
+    RenderTemplate(#[from] handlebars::RenderError),
+
+    #[error("error running LVS: {0}")]
+    Lvs(String),
+
+    #[error("error serializing/deserializing JSON: {0}")]
+    JsonSerialization(#[from] serde_json::Error),
+
+    #[error("file format error: {0}")]
+    FileFormat(String),
+}
+
+pub type Result<T> = std::result::Result<T, EdaToolError>;
diff --git a/sram22/src/verification/mod.rs → edatool/src/lib.rs b/sram22/src/verification/mod.rs → edatool/src/lib.rs
@@ -1,3 +1,4 @@
+pub mod error;
 pub mod lvs;
 pub mod pex;
 pub mod plugins;

diff --git a/sram22/src/verification/lvs/mod.rs → edatool/src/lvs/mod.rs b/sram22/src/verification/lvs/mod.rs → edatool/src/lvs/mod.rs
diff --git a/sram22/src/verification/pex/mod.rs → edatool/src/pex/mod.rs b/sram22/src/verification/pex/mod.rs → edatool/src/pex/mod.rs
diff --git a/edatool/src/plugins/magic_pex b/edatool/src/plugins/magic_pex
diff --git a/sram22/src/verification/plugins/mod.rs → edatool/src/plugins/mod.rs b/sram22/src/verification/plugins/mod.rs → edatool/src/plugins/mod.rs
diff --git a/edatool/src/plugins/netgen_lvs b/edatool/src/plugins/netgen_lvs
diff --git a/...c/verification/plugins/ngspice_sim/mod.rs → edatool/src/plugins/ngspice_sim/mod.rs b/...c/verification/plugins/ngspice_sim/mod.rs → edatool/src/plugins/ngspice_sim/mod.rs
@@ -1,6 +1,6 @@
-use crate::error::{Result, Sram22Error};
-use crate::verification::sim::analysis::{Analysis, AnalysisData, Mode, SpiceData};
-use crate::verification::sim::testbench::{NetlistSource, Testbench};
+use crate::error::{EdaToolError, Result};
+use crate::sim::analysis::{Analysis, AnalysisData, Mode, SpiceData};
+use crate::sim::testbench::{NetlistSource, Testbench};
 use std::collections::HashMap;
 use std::fs::{self, read_to_string, File};
 use std::io::{BufRead, BufReader, Write};
@@ -185,11 +185,11 @@ fn read_analysis_data(a: &Analysis, out_file: impl AsRef<Path>) -> Result<Analys
                 .map(|s| s.parse::<f64>())
                 .collect::<std::result::Result<Vec<_>, _>>()
                 .map_err(|_| {
-                    Sram22Error::FileFormat(
+                    EdaToolError::FileFormat(
                         "invalid output data format from ngspice simulation".to_string(),
                     )
                 })?;
-            Ok::<Vec<f64>, Sram22Error>(row)
+            Ok::<Vec<f64>, EdaToolError>(row)
         })
         .collect::<std::result::Result<Vec<_>, _>>()?;
 
@@ -230,7 +230,7 @@ fn read_analysis_data(a: &Analysis, out_file: impl AsRef<Path>) -> Result<Analys
     }
 
     if results.contains_key("sweep_var") {
-        return Err(Sram22Error::FileFormat(
+        return Err(EdaToolError::FileFormat(
             "cannot have variable named `sweep_var` in results".to_string(),
         ));
     }

diff --git a/...ins/ngspice_sim/tests/data/include1.spice → ...ins/ngspice_sim/tests/data/include1.spice b/...ins/ngspice_sim/tests/data/include1.spice → ...ins/ngspice_sim/tests/data/include1.spice
diff --git a/...ins/ngspice_sim/tests/data/vdivider.spice → ...ins/ngspice_sim/tests/data/vdivider.spice b/...ins/ngspice_sim/tests/data/vdivider.spice → ...ins/ngspice_sim/tests/data/vdivider.spice
diff --git a/...gspice_sim/tests/data/vdivider_tran.spice → ...gspice_sim/tests/data/vdivider_tran.spice b/...gspice_sim/tests/data/vdivider_tran.spice → ...gspice_sim/tests/data/vdivider_tran.spice
diff --git a/...fication/plugins/ngspice_sim/tests/mod.rs → edatool/src/plugins/ngspice_sim/tests/mod.rs b/...fication/plugins/ngspice_sim/tests/mod.rs → edatool/src/plugins/ngspice_sim/tests/mod.rs
@@ -2,7 +2,7 @@ use std::path::PathBuf;
 
 use approx::abs_diff_eq;
 
-use crate::verification::sim::{
+use crate::sim::{
     analysis::{Analysis, TransientAnalysis},
     testbench::{NetlistSource, Testbench},
     waveform::{Waveform, WaveformBuf},
@@ -16,7 +16,7 @@ fn test_ngspice_vdivider() -> Result<(), Box<dyn std::error::Error>> {
     let tb = Testbench::with_source(NetlistSource::File(netlist));
     let mut ngs = Ngspice::with_tb(tb);
     ngs.cwd("/tmp/sram22/tests/sim/vdivider".into());
-    let mut op = Analysis::with_mode(crate::verification::sim::analysis::Mode::Op);
+    let mut op = Analysis::with_mode(crate::sim::analysis::Mode::Op);
     op.save("v(out)");
 
     ngs.add_analysis(op);
@@ -38,7 +38,7 @@ fn test_ngspice_include1() -> Result<(), Box<dyn std::error::Error>> {
     tb.include(include);
     let mut ngs = Ngspice::with_tb(tb);
     ngs.cwd("/tmp/sram22/tests/sim/include1".into());
-    let mut op = Analysis::with_mode(crate::verification::sim::analysis::Mode::Op);
+    let mut op = Analysis::with_mode(crate::sim::analysis::Mode::Op);
     op.save("v(out)");
 
     ngs.add_analysis(op);
@@ -62,14 +62,12 @@ fn test_vdivider_tran() -> Result<(), Box<dyn std::error::Error>> {
     tb.add_waveform(wav);
 
     // Set up analysis
-    let mut tran = Analysis::with_mode(crate::verification::sim::analysis::Mode::Tran(
-        TransientAnalysis {
-            tstart: 0f64,
-            tstep: 1f64,
-            tstop: 4f64,
-            uic: false,
-        },
-    ));
+    let mut tran = Analysis::with_mode(crate::sim::analysis::Mode::Tran(TransientAnalysis {
+        tstart: 0f64,
+        tstep: 1f64,
+        tstop: 4f64,
+        uic: false,
+    }));
     tran.save("v(out)");
 
     // Set up ngspice
@@ -89,6 +87,5 @@ fn test_vdivider_tran() -> Result<(), Box<dyn std::error::Error>> {
 }
 
 fn test_data_path() -> PathBuf {
-    PathBuf::from(env!("CARGO_MANIFEST_DIR"))
-        .join("src/verification/plugins/ngspice_sim/tests/data")
+    PathBuf::from(env!("CARGO_MANIFEST_DIR")).join("src/plugins/ngspice_sim/tests/data")
 }
diff --git a/sram22/src/verification/sim/analysis.rs → edatool/src/sim/analysis.rs b/sram22/src/verification/sim/analysis.rs → edatool/src/sim/analysis.rs
diff --git a/sram22/src/verification/sim/mod.rs → edatool/src/sim/mod.rs b/sram22/src/verification/sim/mod.rs → edatool/src/sim/mod.rs
diff --git a/sram22/src/verification/sim/testbench.rs → edatool/src/sim/testbench.rs b/sram22/src/verification/sim/testbench.rs → edatool/src/sim/testbench.rs
diff --git a/sram22/src/verification/sim/waveform.rs → edatool/src/sim/waveform.rs b/sram22/src/verification/sim/waveform.rs → edatool/src/sim/waveform.rs
@@ -1,4 +1,4 @@
-use crate::{error::Sram22Error, Result};
+use crate::error::{EdaToolError, Result};
 use std::{
     fmt::Display,
     io::{BufRead, BufReader, Read, Write},
@@ -39,7 +39,7 @@ impl<'a> Waveform<'a> {
     where
         T: Write,
     {
-        writeln!(w, "# waveform saved by Sram22")?;
+        writeln!(w, "# waveform saved by edatool")?;
         writeln!(w, "# one output port")?;
         writeln!(w, "# column 1: time (sec)")?;
         writeln!(w, "# column 2: value")?;
@@ -102,7 +102,7 @@ impl WaveformBuf {
     where
         T: Write,
     {
-        writeln!(w, "# waveform saved by Sram22")?;
+        writeln!(w, "# waveform saved by edatool")?;
         writeln!(w, "# one output port")?;
         writeln!(w, "# column 1: time (sec)")?;
         writeln!(w, "# column 2: value")?;
@@ -132,16 +132,16 @@ fn parse_waveform_line(line: &str) -> Result<(f64, f64)> {
     let mut split = line.split_whitespace();
     let t = split
         .next()
-        .ok_or_else(|| Sram22Error::FileFormat("invalid line in waveform".to_string()))?
+        .ok_or_else(|| EdaToolError::FileFormat("invalid line in waveform".to_string()))?
         .parse::<f64>()
-        .map_err(|_| Sram22Error::FileFormat("unexpected value in waveform".to_string()))?;
+        .map_err(|_| EdaToolError::FileFormat("unexpected value in waveform".to_string()))?;
     let y = split
         .next()
-        .ok_or_else(|| Sram22Error::FileFormat("invalid line in waveform".to_string()))?
+        .ok_or_else(|| EdaToolError::FileFormat("invalid line in waveform".to_string()))?
         .parse::<f64>()
-        .map_err(|_| Sram22Error::FileFormat("unexpected value in waveform".to_string()))?;
+        .map_err(|_| EdaToolError::FileFormat("unexpected value in waveform".to_string()))?;
     if split.next().is_some() {
-        return Err(Sram22Error::FileFormat(
+        return Err(EdaToolError::FileFormat(
             "more than two values on the same line in waveform".to_string(),
         ));
     }

diff --git a/sram22/Cargo.toml b/sram22/Cargo.toml
@@ -12,6 +12,7 @@ grid = { version = "*" }
 thiserror = "1.0"
 magic_vlsi = { path = "../magic_vlsi" }
 micro_hdl = { path = "../micro_hdl" }
+edatool = { path = "../edatool" }
 serde = { version = "1.0", features = ["derive"] }
 serde_json = "1.0"
 toml = "0.5.8"

diff --git a/sram22/src/cells/gates/nand/tests/mod.rs b/sram22/src/cells/gates/nand/tests/mod.rs
@@ -1,15 +1,11 @@
-use crate::{
-    cells::gates::GateSize,
-    sky130_config, tech_spice_include,
-    test_utils::get_magic,
-    verification::{
-        pex::{Pex, PexInput, PexOpts},
-        plugins::{magic_pex::MagicPex, ngspice_sim::Ngspice},
-        sim::{
-            analysis::{Analysis, TransientAnalysis},
-            testbench::{NetlistSource, Testbench},
-            waveform::{Waveform, WaveformBuf},
-        },
+use crate::{cells::gates::GateSize, sky130_config, tech_spice_include, test_utils::get_magic};
+use edatool::{
+    pex::{Pex, PexInput, PexOpts},
+    plugins::{magic_pex::MagicPex, ngspice_sim::Ngspice},
+    sim::{
+        analysis::{Analysis, TransientAnalysis},
+        testbench::{NetlistSource, Testbench},
+        waveform::{Waveform, WaveformBuf},
     },
 };
 use std::{
@@ -92,14 +88,8 @@ fn test_simulate_pex_nand2() -> Result<(), Box<dyn std::error::Error>> {
     tb.add_waveform(va);
     tb.add_waveform(vb);
 
-    let mut tran = Analysis::with_mode(crate::verification::sim::analysis::Mode::Tran(
-        TransientAnalysis {
-            tstart: 0f64,
-            tstep: 1f64,
-            tstop: 4f64,
-            uic: false,
-        },
-    ));
+    let tran = TransientAnalysis::new(4f64).tstep(1f64);
+    let mut tran = Analysis::with_mode(edatool::sim::analysis::Mode::Tran(tran));
     tran.save("v(a)");
     tran.save("v(b)");
     tran.save("v(y)");

diff --git a/sram22/src/lib.rs b/sram22/src/lib.rs
@@ -23,7 +23,6 @@ pub mod error;
 pub mod layout;
 pub mod precharge;
 pub mod predecode;
-pub mod verification;
 
 pub fn generate(config: SramConfig) -> Result<()> {
     let rows = config.rows;

diff --git a/sram22/src/verification/plugins/magic_pex b/sram22/src/verification/plugins/magic_pex
diff --git a/sram22/src/verification/plugins/netgen_lvs b/sram22/src/verification/plugins/netgen_lvs