From 92e1dcd72359b5cee461bddf9275011daeed1a38 Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Mon, 1 Mar 2021 04:27:45 +1100 Subject: [PATCH 01/24] initial L433 commit --- .../GENERIC_STM32_L433xB/board/board.mk | 9 +++++ .../GENERIC_STM32_L433xB/configs/board.h | 20 +++++++++++ .../GENERIC_STM32_L433xB/configs/config.h | 25 +++++++++++++ quantum/mcu_selection.mk | 35 +++++++++++++++++++ 4 files changed, 89 insertions(+) create mode 100644 platforms/chibios/GENERIC_STM32_L433xB/board/board.mk create mode 100644 platforms/chibios/GENERIC_STM32_L433xB/configs/board.h create mode 100644 platforms/chibios/GENERIC_STM32_L433xB/configs/config.h diff --git a/platforms/chibios/GENERIC_STM32_L433xB/board/board.mk b/platforms/chibios/GENERIC_STM32_L433xB/board/board.mk new file mode 100644 index 000000000000..aaf4ed068c9d --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_L433xB/board/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC/board.c + +# Required include directories +BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/platforms/chibios/GENERIC_STM32_L433xB/configs/board.h b/platforms/chibios/GENERIC_STM32_L433xB/configs/board.h new file mode 100644 index 000000000000..30af6b0c8608 --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_L433xB/configs/board.h @@ -0,0 +1,20 @@ +/* Copyright 2020 Nick Brassel (tzarc) + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#pragma once + +#include_next "board.h" + +#undef STM32_HSE_BYPASS diff --git a/platforms/chibios/GENERIC_STM32_L433xB/configs/config.h b/platforms/chibios/GENERIC_STM32_L433xB/configs/config.h new file mode 100644 index 000000000000..d2b254f92761 --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_L433xB/configs/config.h @@ -0,0 +1,25 @@ +/* Copyright 2018-2020 Nick Brassel (@tzarc) + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Address for jumping to bootloader on STM32 chips. */ +/* It is chip dependent, the correct number can be looked up here (page 175): + * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf + * This also requires a patch to chibios: + * /tmk_core/tool/chibios/ch-bootloader-jump.patch + */ +#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000 + +#define PAL_STM32_OSPEED_HIGHEST PAL_STM32_OSPEED_HIGH diff --git a/quantum/mcu_selection.mk b/quantum/mcu_selection.mk index edf44f5dcc6a..0ecd6bcf9934 100644 --- a/quantum/mcu_selection.mk +++ b/quantum/mcu_selection.mk @@ -435,6 +435,41 @@ ifneq ($(findstring STM32G474, $(MCU)),) UF2_FAMILY ?= STM32G4 endif +ifneq ($(findstring STM32L433xB, $(MCU)),) + # Cortex version + MCU = cortex-m4 + + # ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7 + ARMV = 7 + + ## chip/board settings + # - the next two should match the directories in + # /os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES) + MCU_FAMILY = STM32 + MCU_SERIES = STM32L4xx + + # Linker script to use + # - it should exist either in /os/common/ports/ARMCMx/compilers/GCC/ld/ + # or /ld/ + MCU_LDSCRIPT ?= STM32L432xB + + # Startup code to use + # - it should exist in /os/common/startup/ARMCMx/compilers/GCC/mk/ + MCU_STARTUP ?= stm32l4xx + + # Board: it should exist either in /os/hal/boards/, + # /boards/, or drivers/boards/ + BOARD ?= GENERIC_STM32_L433xB + + PLATFORM_NAME ?= platform_l432 + + USE_FPU ?= yes + + # Options to pass to dfu-util when flashing + DFU_ARGS ?= -d 0483:DF11 -a 0 -s 0x08000000:leave + DFU_SUFFIX_ARGS ?= -v 0483 -p DF11 +endif + ifneq (,$(filter $(MCU),at90usb162 atmega16u2 atmega32u2 atmega16u4 atmega32u4 at90usb646 at90usb647 at90usb1286 at90usb1287)) PROTOCOL = LUFA From f056c289738de113a6ed97cee46df8252b37be2c Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Mon, 1 Mar 2021 04:50:23 +1100 Subject: [PATCH 02/24] change to XC --- docs/compatible_microcontrollers.md | 1 + docs/ja/compatible_microcontrollers.md | 1 + lib/python/qmk/constants.py | 2 +- .../board/board.mk | 0 .../configs/board.h | 2 +- .../configs/config.h | 2 +- .../GENERIC_STM32_L433XC/configs/mcuconf.h | 263 ++++++++++++++++++ quantum/mcu_selection.mk | 6 +- 8 files changed, 271 insertions(+), 6 deletions(-) rename platforms/chibios/{GENERIC_STM32_L433xB => GENERIC_STM32_L433XC}/board/board.mk (100%) rename platforms/chibios/{GENERIC_STM32_L433xB => GENERIC_STM32_L433XC}/configs/board.h (94%) rename platforms/chibios/{GENERIC_STM32_L433xB => GENERIC_STM32_L433XC}/configs/config.h (95%) create mode 100644 platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h diff --git a/docs/compatible_microcontrollers.md b/docs/compatible_microcontrollers.md index 5e16ab277017..f04748a85289 100644 --- a/docs/compatible_microcontrollers.md +++ b/docs/compatible_microcontrollers.md @@ -31,6 +31,7 @@ You can also use any ARM chip with USB that [ChibiOS](https://www.chibios.org) s * [STM32F446](https://www.st.com/en/microcontrollers-microprocessors/stm32f446.html) * [STM32G431](https://www.st.com/en/microcontrollers-microprocessors/stm32g4x1.html) * [STM32G474](https://www.st.com/en/microcontrollers-microprocessors/stm32g4x4.html) + * [STM32L433](https://www.st.com/en/microcontrollers-microprocessors/stm32l4x3.html) ### NXP (Kinetis) diff --git a/docs/ja/compatible_microcontrollers.md b/docs/ja/compatible_microcontrollers.md index 69da70f2c31d..d86941c72ab6 100644 --- a/docs/ja/compatible_microcontrollers.md +++ b/docs/ja/compatible_microcontrollers.md @@ -36,6 +36,7 @@ QMK は十分な容量のフラッシュメモリを備えた USB 対応 AVR ま * [STM32F446](https://www.st.com/en/microcontrollers-microprocessors/stm32f446.html) * [STM32G431](https://www.st.com/en/microcontrollers-microprocessors/stm32g4x1.html) * [STM32G474](https://www.st.com/en/microcontrollers-microprocessors/stm32g4x4.html) +* [STM32L433](https://www.st.com/en/microcontrollers-microprocessors/stm32l4x3.html) ### NXP (Kinetis) diff --git a/lib/python/qmk/constants.py b/lib/python/qmk/constants.py index 33adb0a13e4d..394801cb53ff 100644 --- a/lib/python/qmk/constants.py +++ b/lib/python/qmk/constants.py @@ -10,7 +10,7 @@ MAX_KEYBOARD_SUBFOLDERS = 5 # Supported processor types -CHIBIOS_PROCESSORS = 'cortex-m0', 'cortex-m0plus', 'cortex-m3', 'cortex-m4', 'MKL26Z64', 'MK20DX128', 'MK20DX256', 'MK66F18', 'STM32F042', 'STM32F072', 'STM32F103', 'STM32F303', 'STM32F401', 'STM32F411', 'STM32F446', 'STM32G431', 'STM32G474' +CHIBIOS_PROCESSORS = 'cortex-m0', 'cortex-m0plus', 'cortex-m3', 'cortex-m4', 'MKL26Z64', 'MK20DX128', 'MK20DX256', 'MK66F18', 'STM32F042', 'STM32F072', 'STM32F103', 'STM32F303', 'STM32F401', 'STM32F411', 'STM32F446', 'STM32G431', 'STM32G474', 'STM32L433' LUFA_PROCESSORS = 'at90usb162', 'atmega16u2', 'atmega32u2', 'atmega16u4', 'atmega32u4', 'at90usb646', 'at90usb647', 'at90usb1286', 'at90usb1287', None VUSB_PROCESSORS = 'atmega32a', 'atmega328p', 'atmega328', 'attiny85' diff --git a/platforms/chibios/GENERIC_STM32_L433xB/board/board.mk b/platforms/chibios/GENERIC_STM32_L433XC/board/board.mk similarity index 100% rename from platforms/chibios/GENERIC_STM32_L433xB/board/board.mk rename to platforms/chibios/GENERIC_STM32_L433XC/board/board.mk diff --git a/platforms/chibios/GENERIC_STM32_L433xB/configs/board.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h similarity index 94% rename from platforms/chibios/GENERIC_STM32_L433xB/configs/board.h rename to platforms/chibios/GENERIC_STM32_L433XC/configs/board.h index 30af6b0c8608..1e2670c1e6cb 100644 --- a/platforms/chibios/GENERIC_STM32_L433xB/configs/board.h +++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h @@ -1,4 +1,4 @@ -/* Copyright 2020 Nick Brassel (tzarc) +/* Copyright 2018-2021 Harrison Chan (@Xelus) * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/platforms/chibios/GENERIC_STM32_L433xB/configs/config.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/config.h similarity index 95% rename from platforms/chibios/GENERIC_STM32_L433xB/configs/config.h rename to platforms/chibios/GENERIC_STM32_L433XC/configs/config.h index d2b254f92761..05e53d65e355 100644 --- a/platforms/chibios/GENERIC_STM32_L433xB/configs/config.h +++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/config.h @@ -1,4 +1,4 @@ -/* Copyright 2018-2020 Nick Brassel (@tzarc) +/* Copyright 2018-2021 Harrison Chan (@Xelus) * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h new file mode 100644 index 000000000000..c0edf4f45b97 --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h @@ -0,0 +1,263 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + http://www.apache.org/licenses/LICENSE-2.0 + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32L4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define STM32L4xx_MCUCONF +#define STM32L432_MCUCONF +#define STM32L433_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_RANGE1 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI16_ENABLED TRUE +#define STM32_HSI48_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED FALSE +#define STM32_MSIPLL_ENABLED FALSE +#define STM32_MSIRANGE STM32_MSIRANGE_4M +#define STM32_MSISRANGE STM32_MSISRANGE_4M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_MSI +#define STM32_PLLM_VALUE 1 +#define STM32_PLLN_VALUE 36 +#define STM32_PLLPDIV_VALUE 0 +#define STM32_PLLP_VALUE 7 +#define STM32_PLLQ_VALUE 2 +#define STM32_PLLR_VALUE 2 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_STOPWUCK STM32_STOPWUCK_MSI +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK +#define STM32_PLLSAI1N_VALUE 24 +#define STM32_PLLSAI1PDIV_VALUE 0 +#define STM32_PLLSAI1P_VALUE 7 +#define STM32_PLLSAI1Q_VALUE 2 +#define STM32_PLLSAI1R_VALUE 2 + +/* + * Peripherals clock sources. + */ +#define STM32_USART1SEL STM32_USART1SEL_SYSCLK +#define STM32_USART2SEL STM32_USART2SEL_SYSCLK +#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK +#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK +#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 +#define STM32_ADCSEL STM32_ADCSEL_SYSCLK +#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 +#define STM32_RTCSEL STM32_RTCSEL_LSI + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI1635_38_PRIORITY 6 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_22_PRIORITY 15 + +#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7 +#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7 +#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 +#define STM32_IRQ_TIM7_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_LPUART1_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_COMPACT_SAMPLES FALSE +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM15 FALSE +#define STM32_GPT_USE_TIM16 FALSE + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM15 FALSE +#define STM32_ICU_USE_TIM16 FALSE + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM15 TRUE +#define STM32_PWM_USE_TIM16 FALSE + +/* + * RTC driver system settings. + */ +#define STM32_RTC_PRESA_VALUE 32 +#define STM32_RTC_PRESS_VALUE 1024 +#define STM32_RTC_CR_INIT 0 +#define STM32_RTC_TAMPCR_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_LPUART1 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_LPUART1_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * TRNG driver system settings. + */ +#define STM32_TRNG_USE_RNG1 FALSE + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +/* + * WSPI driver system settings. + */ +#define STM32_WSPI_USE_QUADSPI1 FALSE +#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) + +#endif /* MCUCONF_H */ diff --git a/quantum/mcu_selection.mk b/quantum/mcu_selection.mk index 0ecd6bcf9934..e73f7a780240 100644 --- a/quantum/mcu_selection.mk +++ b/quantum/mcu_selection.mk @@ -435,7 +435,7 @@ ifneq ($(findstring STM32G474, $(MCU)),) UF2_FAMILY ?= STM32G4 endif -ifneq ($(findstring STM32L433xB, $(MCU)),) +ifneq ($(findstring STM32L433, $(MCU)),) # Cortex version MCU = cortex-m4 @@ -451,7 +451,7 @@ ifneq ($(findstring STM32L433xB, $(MCU)),) # Linker script to use # - it should exist either in /os/common/ports/ARMCMx/compilers/GCC/ld/ # or /ld/ - MCU_LDSCRIPT ?= STM32L432xB + MCU_LDSCRIPT ?= STM32L432xC # Startup code to use # - it should exist in /os/common/startup/ARMCMx/compilers/GCC/mk/ @@ -459,7 +459,7 @@ ifneq ($(findstring STM32L433xB, $(MCU)),) # Board: it should exist either in /os/hal/boards/, # /boards/, or drivers/boards/ - BOARD ?= GENERIC_STM32_L433xB + BOARD ?= GENERIC_STM32_L433XC PLATFORM_NAME ?= platform_l432 From a3706371904aa100f07f5a60f0d45859742e0660 Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Mon, 1 Mar 2021 05:37:18 +1100 Subject: [PATCH 03/24] fix L433 --- data/schemas/keyboard.jsonschema | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/data/schemas/keyboard.jsonschema b/data/schemas/keyboard.jsonschema index 99121d79eca3..77ef174773e0 100644 --- a/data/schemas/keyboard.jsonschema +++ b/data/schemas/keyboard.jsonschema @@ -25,7 +25,7 @@ }, "processor": { "type": "string", - "enum": ["cortex-m0", "cortex-m0plus", "cortex-m3", "cortex-m4", "MKL26Z64", "MK20DX128", "MK20DX256", "MK66F18", "STM32F042", "STM32F072", "STM32F103", "STM32F303", "STM32F401", "STM32F411", "STM32F446", "STM32G431", "STM32G474", "atmega16u2", "atmega32u2", "atmega16u4", "atmega32u4", "at90usb162", "at90usb646", "at90usb647", "at90usb1286", "at90usb1287", "atmega32a", "atmega328p", "atmega328", "attiny85", "unknown"] + "enum": ["cortex-m0", "cortex-m0plus", "cortex-m3", "cortex-m4", "MKL26Z64", "MK20DX128", "MK20DX256", "MK66F18", "STM32F042", "STM32F072", "STM32F103", "STM32F303", "STM32F401", "STM32F411", "STM32F446", "STM32G431", "STM32G474", "STM32L433", "atmega16u2", "atmega32u2", "atmega16u4", "atmega32u4", "at90usb162", "at90usb646", "at90usb647", "at90usb1286", "at90usb1287", "atmega32a", "atmega328p", "atmega328", "attiny85", "unknown"] }, "board": { "type": "string", From 2b9544550fc7cc176cdf1e88a7a27a02870d31f6 Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Mon, 1 Mar 2021 07:17:54 +1100 Subject: [PATCH 04/24] disable all peripherals --- platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h index c0edf4f45b97..869eb2fb6d27 100644 --- a/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h +++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h @@ -156,7 +156,7 @@ /* * I2C driver system settings. */ -#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C1 FALSE #define STM32_I2C_USE_I2C3 FALSE #define STM32_I2C_BUSY_TIMEOUT 50 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) @@ -183,7 +183,7 @@ #define STM32_PWM_USE_ADVANCED FALSE #define STM32_PWM_USE_TIM1 FALSE #define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM15 TRUE +#define STM32_PWM_USE_TIM15 FALSE #define STM32_PWM_USE_TIM16 FALSE /* @@ -198,7 +198,7 @@ * SERIAL driver system settings. */ #define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART2 FALSE #define STM32_SERIAL_USE_LPUART1 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 From 2224e54cf1c152eba999e32daa482385a8833a72 Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Mon, 1 Mar 2021 07:33:24 +1100 Subject: [PATCH 05/24] update system and peripheral clocks --- platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h index 869eb2fb6d27..b45a396f0b65 100644 --- a/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h +++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h @@ -48,9 +48,9 @@ #define STM32_MSIRANGE STM32_MSIRANGE_4M #define STM32_MSISRANGE STM32_MSISRANGE_4M #define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_MSI +#define STM32_PLLSRC STM32_PLLSRC_HSI16 #define STM32_PLLM_VALUE 1 -#define STM32_PLLN_VALUE 36 +#define STM32_PLLN_VALUE 10 #define STM32_PLLPDIV_VALUE 0 #define STM32_PLLP_VALUE 7 #define STM32_PLLQ_VALUE 2 @@ -79,7 +79,7 @@ #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 #define STM32_SAI1SEL STM32_SAI1SEL_OFF -#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 +#define STM32_CLK48SEL STM32_CLK48SEL_HSI48 #define STM32_ADCSEL STM32_ADCSEL_SYSCLK #define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 #define STM32_RTCSEL STM32_RTCSEL_LSI From b14b3723bcb401e74d7f1bd1ac5e64164a1b332f Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Wed, 10 Mar 2021 21:15:44 +1100 Subject: [PATCH 06/24] 433 change --- platforms/chibios/GENERIC_STM32_L433XC/configs/board.h | 2 ++ platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h | 1 - 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h index 1e2670c1e6cb..f8f0369df85c 100644 --- a/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h +++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h @@ -18,3 +18,5 @@ #include_next "board.h" #undef STM32_HSE_BYPASS + +#define STM32L433xx diff --git a/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h index b45a396f0b65..68ad3b647c93 100644 --- a/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h +++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h @@ -29,7 +29,6 @@ #define MCUCONF_H #define STM32L4xx_MCUCONF -#define STM32L432_MCUCONF #define STM32L433_MCUCONF /* From 6ebfabb21f39f94680294a8bc8555dbc7582628a Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Wed, 10 Mar 2021 21:38:18 +1100 Subject: [PATCH 07/24] use its own board files --- .../GENERIC_STM32_L433XC/board/board.c | 281 ++++ .../GENERIC_STM32_L433XC/board/board.h | 1486 +++++++++++++++++ .../GENERIC_STM32_L433XC/board/board.mk | 6 +- 3 files changed, 1770 insertions(+), 3 deletions(-) create mode 100644 platforms/chibios/GENERIC_STM32_L433XC/board/board.c create mode 100644 platforms/chibios/GENERIC_STM32_L433XC/board/board.h diff --git a/platforms/chibios/GENERIC_STM32_L433XC/board/board.c b/platforms/chibios/GENERIC_STM32_L433XC/board/board.c new file mode 100644 index 000000000000..fceb3fdec6c3 --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_L433XC/board/board.c @@ -0,0 +1,281 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; + uint32_t ascr; + uint32_t lockr; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR, + VAL_GPIOA_LOCKR}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR, + VAL_GPIOB_LOCKR}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR, + VAL_GPIOC_LOCKR}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR, + VAL_GPIOD_LOCKR}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR, + VAL_GPIOE_LOCKR}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR, + VAL_GPIOF_LOCKR}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR, + VAL_GPIOG_LOCKR}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR, + VAL_GPIOH_LOCKR}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR, + VAL_GPIOI_LOCKR}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR, + VAL_GPIOJ_LOCKR}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR, + VAL_GPIOK_LOCKR} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->ASCR = config->ascr; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; + gpiop->LOCKR = config->lockr; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB2(STM32_GPIO_EN_MASK); + rccEnableAHB2(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* CHTODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* CHTODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* CHTODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* CHTODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @note You can add your board-specific code here. + */ +void boardInit(void) { + +} diff --git a/platforms/chibios/GENERIC_STM32_L433XC/board/board.h b/platforms/chibios/GENERIC_STM32_L433XC/board/board.h new file mode 100644 index 000000000000..35d136d088a8 --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_L433XC/board/board.h @@ -0,0 +1,1486 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup for STMicroelectronics STM32 Nucleo32-L432KC board. + */ + +/* + * Board identifier. + */ +#define BOARD_GENERIC_STM32_L433XC +#define BOARD_NAME "Generic STM32L433 PCB" + +/* + * Board oscillators-related settings. + * NOTE: HSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#define STM32_LSEDRV (2U << 3U) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 0U +#endif + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32L433xx + +/* + * IO pins assignments. + */ +#define GPIOA_ARD_A0 0U +#define GPIOA_ARD_A1 1U +#define GPIOA_VCP_TX 2U +#define GPIOA_ARD_A2 3U +#define GPIOA_ARD_A3 4U +#define GPIOA_ARD_A4 5U +#define GPIOA_ARD_A5 6U +#define GPIOA_ARD_A6 7U +#define GPIOA_ARD_D9 8U +#define GPIOA_ARD_D1 9U +#define GPIOA_ARD_D0 10U +#define GPIOA_ARD_D10 11U +#define GPIOA_ARD_D2 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_VCP_RX 15U + +#define GPIOB_ARD_D3 0U +#define GPIOB_ARD_D6 1U +#define GPIOB_PIN2 2U +#define GPIOB_ARD_D13 3U +#define GPIOB_LED_GREEN 3U +#define GPIOB_ARD_D12 4U +#define GPIOB_ARD_D11 5U +#define GPIOB_ARD_D5 6U +#define GPIOB_ARD_A5_ALT 6U +#define GPIOB_ARD_D4 7U +#define GPIOB_ARD_A4_ALT 7U +#define GPIOB_PIN8 8U +#define GPIOB_PIN9 9U +#define GPIOB_PIN10 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U + +#define GPIOC_PIN0 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_PIN7 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_ARD_D7 14U +#define GPIOC_ARD_D8 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U + +#define GPIOE_PIN0 0U +#define GPIOE_PIN1 1U +#define GPIOE_PIN2 2U +#define GPIOE_PIN3 3U +#define GPIOE_PIN4 4U +#define GPIOE_PIN5 5U +#define GPIOE_PIN6 6U +#define GPIOE_PIN7 7U +#define GPIOE_PIN8 8U +#define GPIOE_PIN9 9U +#define GPIOE_PIN10 10U +#define GPIOE_PIN11 11U +#define GPIOE_PIN12 12U +#define GPIOE_PIN13 13U +#define GPIOE_PIN14 14U +#define GPIOE_PIN15 15U + +#define GPIOF_PIN0 0U +#define GPIOF_PIN1 1U +#define GPIOF_PIN2 2U +#define GPIOF_PIN3 3U +#define GPIOF_PIN4 4U +#define GPIOF_PIN5 5U +#define GPIOF_PIN6 6U +#define GPIOF_PIN7 7U +#define GPIOF_PIN8 8U +#define GPIOF_PIN9 9U +#define GPIOF_PIN10 10U +#define GPIOF_PIN11 11U +#define GPIOF_PIN12 12U +#define GPIOF_PIN13 13U +#define GPIOF_PIN14 14U +#define GPIOF_PIN15 15U + +#define GPIOG_PIN0 0U +#define GPIOG_PIN1 1U +#define GPIOG_PIN2 2U +#define GPIOG_PIN3 3U +#define GPIOG_PIN4 4U +#define GPIOG_PIN5 5U +#define GPIOG_PIN6 6U +#define GPIOG_PIN7 7U +#define GPIOG_PIN8 8U +#define GPIOG_PIN9 9U +#define GPIOG_PIN10 10U +#define GPIOG_PIN11 11U +#define GPIOG_PIN12 12U +#define GPIOG_PIN13 13U +#define GPIOG_PIN14 14U +#define GPIOG_PIN15 15U + +#define GPIOH_PIN0 0U +#define GPIOH_PIN1 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U) +#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U) +#define LINE_VCP_TX PAL_LINE(GPIOA, 2U) +#define LINE_ARD_A2 PAL_LINE(GPIOA, 3U) +#define LINE_ARD_A3 PAL_LINE(GPIOA, 4U) +#define LINE_ARD_A4 PAL_LINE(GPIOA, 5U) +#define LINE_ARD_A5 PAL_LINE(GPIOA, 6U) +#define LINE_ARD_A6 PAL_LINE(GPIOA, 7U) +#define LINE_ARD_D9 PAL_LINE(GPIOA, 8U) +#define LINE_ARD_D1 PAL_LINE(GPIOA, 9U) +#define LINE_ARD_D0 PAL_LINE(GPIOA, 10U) +#define LINE_ARD_D10 PAL_LINE(GPIOA, 11U) +#define LINE_ARD_D2 PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_VCP_RX PAL_LINE(GPIOA, 15U) +#define LINE_ARD_D3 PAL_LINE(GPIOB, 0U) +#define LINE_ARD_D6 PAL_LINE(GPIOB, 1U) +#define LINE_ARD_D13 PAL_LINE(GPIOB, 3U) +#define LINE_LED_GREEN PAL_LINE(GPIOB, 3U) +#define LINE_ARD_D12 PAL_LINE(GPIOB, 4U) +#define LINE_ARD_D11 PAL_LINE(GPIOB, 5U) +#define LINE_ARD_D5 PAL_LINE(GPIOB, 6U) +#define LINE_ARD_A5_ALT PAL_LINE(GPIOB, 6U) +#define LINE_ARD_D4 PAL_LINE(GPIOB, 7U) +#define LINE_ARD_A4_ALT PAL_LINE(GPIOB, 7U) +#define LINE_ARD_D7 PAL_LINE(GPIOC, 14U) +#define LINE_ARD_D8 PAL_LINE(GPIOC, 15U) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) +#define PIN_ASCR_DISABLED(n) (0U << (n)) +#define PIN_ASCR_ENABLED(n) (1U << (n)) +#define PIN_LOCKR_DISABLED(n) (0U << (n)) +#define PIN_LOCKR_ENABLED(n) (1U << (n)) + +/* + * GPIOA setup: + * + * PA0 - ARD_A0 (analog). + * PA1 - ARD_A1 (analog). + * PA2 - VCP_TX (alternate 7). + * PA3 - ARD_A2 (analog). + * PA4 - ARD_A3 (analog). + * PA5 - ARD_A4 (analog). + * PA6 - ARD_A5 (analog). + * PA7 - ARD_A6 (analog). + * PA8 - ARD_D9 (analog). + * PA9 - ARD_D1 (analog). + * PA10 - ARD_D0 (analog). + * PA11 - ARD_D10 (analog). + * PA12 - ARD_D2 (analog). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - VCP_RX (alternate 3). + */ +#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_ARD_A0) | \ + PIN_MODE_ANALOG(GPIOA_ARD_A1) | \ + PIN_MODE_ALTERNATE(GPIOA_VCP_TX) | \ + PIN_MODE_ANALOG(GPIOA_ARD_A2) | \ + PIN_MODE_ANALOG(GPIOA_ARD_A3) | \ + PIN_MODE_ANALOG(GPIOA_ARD_A4) | \ + PIN_MODE_ANALOG(GPIOA_ARD_A5) | \ + PIN_MODE_ANALOG(GPIOA_ARD_A6) | \ + PIN_MODE_ANALOG(GPIOA_ARD_D9) | \ + PIN_MODE_ANALOG(GPIOA_ARD_D1) | \ + PIN_MODE_ANALOG(GPIOA_ARD_D0) | \ + PIN_MODE_ANALOG(GPIOA_ARD_D10) | \ + PIN_MODE_ANALOG(GPIOA_ARD_D2) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_ALTERNATE(GPIOA_VCP_RX)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_VCP_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A6) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D9) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_VCP_RX)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \ + PIN_OSPEED_MEDIUM(GPIOA_VCP_TX) | \ + PIN_OSPEED_MEDIUM(GPIOA_ARD_A2) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A3) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A4) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A5) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A6) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D9) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D1) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D0) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D10) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_VCP_RX)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_ARD_A0) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_A1) | \ + PIN_PUPDR_FLOATING(GPIOA_VCP_TX) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_A2) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_A3) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_A4) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_A5) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_A6) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D9) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D1) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D0) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D10) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D2) | \ + PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ + PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ + PIN_PUPDR_FLOATING(GPIOA_VCP_RX)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \ + PIN_ODR_HIGH(GPIOA_ARD_A1) | \ + PIN_ODR_HIGH(GPIOA_VCP_TX) | \ + PIN_ODR_HIGH(GPIOA_ARD_A2) | \ + PIN_ODR_HIGH(GPIOA_ARD_A3) | \ + PIN_ODR_HIGH(GPIOA_ARD_A4) | \ + PIN_ODR_HIGH(GPIOA_ARD_A5) | \ + PIN_ODR_HIGH(GPIOA_ARD_A6) | \ + PIN_ODR_HIGH(GPIOA_ARD_D9) | \ + PIN_ODR_HIGH(GPIOA_ARD_D1) | \ + PIN_ODR_HIGH(GPIOA_ARD_D0) | \ + PIN_ODR_HIGH(GPIOA_ARD_D10) | \ + PIN_ODR_HIGH(GPIOA_ARD_D2) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_VCP_RX)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \ + PIN_AFIO_AF(GPIOA_VCP_TX, 7U) | \ + PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_A3, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_A4, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_A5, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_A6, 0U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D9, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D1, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D0, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D10, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_VCP_RX, 3U)) +#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_ARD_A0) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_A1) | \ + PIN_ASCR_DISABLED(GPIOA_VCP_TX) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_A2) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_A3) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_A4) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_A5) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_A6) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D9) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D1) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D0) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D10) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D2) | \ + PIN_ASCR_DISABLED(GPIOA_SWDIO) | \ + PIN_ASCR_DISABLED(GPIOA_SWCLK) | \ + PIN_ASCR_DISABLED(GPIOA_VCP_RX)) +#define VAL_GPIOA_LOCKR (PIN_LOCKR_DISABLED(GPIOA_ARD_A0) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_A1) | \ + PIN_LOCKR_DISABLED(GPIOA_VCP_TX) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_A2) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_A3) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_A4) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_A5) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_A6) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D9) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D1) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D0) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D10) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D2) | \ + PIN_LOCKR_DISABLED(GPIOA_SWDIO) | \ + PIN_LOCKR_DISABLED(GPIOA_SWCLK) | \ + PIN_LOCKR_DISABLED(GPIOA_VCP_RX)) + +/* + * GPIOB setup: + * + * PB0 - ARD_D3 (input pullup). + * PB1 - ARD_D6 (analog). + * PB2 - PIN2 (analog). + * PB3 - ARD_D13 LED_GREEN (output pushpull maximum). + * PB4 - ARD_D12 (analog). + * PB5 - ARD_D11 (analog). + * PB6 - ARD_D5 ARD_A5_ALT (analog). + * PB7 - ARD_D4 ARD_A4_ALT (analog). + * PB8 - PIN8 (analog). + * PB9 - PIN9 (analog). + * PB10 - PIN10 (analog). + * PB11 - PIN11 (analog). + * PB12 - PIN12 (analog). + * PB13 - PIN13 (analog). + * PB14 - PIN14 (analog). + * PB15 - PIN15 (analog). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_ARD_D3) | \ + PIN_MODE_ANALOG(GPIOB_ARD_D6) | \ + PIN_MODE_ANALOG(GPIOB_PIN2) | \ + PIN_MODE_OUTPUT(GPIOB_ARD_D13) | \ + PIN_MODE_ANALOG(GPIOB_ARD_D12) | \ + PIN_MODE_ANALOG(GPIOB_ARD_D11) | \ + PIN_MODE_ANALOG(GPIOB_ARD_D5) | \ + PIN_MODE_ANALOG(GPIOB_ARD_D4) | \ + PIN_MODE_ANALOG(GPIOB_PIN8) | \ + PIN_MODE_ANALOG(GPIOB_PIN9) | \ + PIN_MODE_ANALOG(GPIOB_PIN10) | \ + PIN_MODE_ANALOG(GPIOB_PIN11) | \ + PIN_MODE_ANALOG(GPIOB_PIN12) | \ + PIN_MODE_ANALOG(GPIOB_PIN13) | \ + PIN_MODE_ANALOG(GPIOB_PIN14) | \ + PIN_MODE_ANALOG(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ARD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ARD_D3) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D6) | \ + PIN_OSPEED_HIGH(GPIOB_PIN2) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D13) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D12) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D11) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D5) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D4) | \ + PIN_OSPEED_HIGH(GPIOB_PIN8) | \ + PIN_OSPEED_HIGH(GPIOB_PIN9) | \ + PIN_OSPEED_HIGH(GPIOB_PIN10) | \ + PIN_OSPEED_HIGH(GPIOB_PIN11) | \ + PIN_OSPEED_HIGH(GPIOB_PIN12) | \ + PIN_OSPEED_HIGH(GPIOB_PIN13) | \ + PIN_OSPEED_HIGH(GPIOB_PIN14) | \ + PIN_OSPEED_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_ARD_D3) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D6) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D13) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D12) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D11) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D5) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D4) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ARD_D3) | \ + PIN_ODR_HIGH(GPIOB_ARD_D6) | \ + PIN_ODR_HIGH(GPIOB_PIN2) | \ + PIN_ODR_LOW(GPIOB_ARD_D13) | \ + PIN_ODR_HIGH(GPIOB_ARD_D12) | \ + PIN_ODR_HIGH(GPIOB_ARD_D11) | \ + PIN_ODR_HIGH(GPIOB_ARD_D5) | \ + PIN_ODR_HIGH(GPIOB_ARD_D4) | \ + PIN_ODR_HIGH(GPIOB_PIN8) | \ + PIN_ODR_HIGH(GPIOB_PIN9) | \ + PIN_ODR_HIGH(GPIOB_PIN10) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_HIGH(GPIOB_PIN13) | \ + PIN_ODR_HIGH(GPIOB_PIN14) | \ + PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_D3, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D13, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D12, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D11, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D4, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0U)) +#define VAL_GPIOB_ASCR (PIN_ASCR_DISABLED(GPIOB_ARD_D3) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D6) | \ + PIN_ASCR_DISABLED(GPIOB_PIN2) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D13) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D12) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D11) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D5) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D4) | \ + PIN_ASCR_DISABLED(GPIOB_PIN8) | \ + PIN_ASCR_DISABLED(GPIOB_PIN9) | \ + PIN_ASCR_DISABLED(GPIOB_PIN10) | \ + PIN_ASCR_DISABLED(GPIOB_PIN11) | \ + PIN_ASCR_DISABLED(GPIOB_PIN12) | \ + PIN_ASCR_DISABLED(GPIOB_PIN13) | \ + PIN_ASCR_DISABLED(GPIOB_PIN14) | \ + PIN_ASCR_DISABLED(GPIOB_PIN15)) +#define VAL_GPIOB_LOCKR (PIN_LOCKR_DISABLED(GPIOB_ARD_D3) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D6) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D13) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D12) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D11) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D5) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D4) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN15)) + +/* + * GPIOC setup: + * + * PC0 - PIN0 (analog). + * PC1 - PIN1 (analog). + * PC2 - PIN2 (analog). + * PC3 - PIN3 (analog). + * PC4 - PIN4 (analog). + * PC5 - PIN5 (analog). + * PC6 - PIN6 (analog). + * PC7 - PIN7 (analog). + * PC8 - PIN8 (analog). + * PC9 - PIN9 (analog). + * PC10 - PIN10 (analog). + * PC11 - PIN11 (analog). + * PC12 - PIN12 (analog). + * PC13 - PIN13 (analog). + * PC14 - ARD_D7 (analog). + * PC15 - ARD_D8 (analog). + */ +#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_PIN0) | \ + PIN_MODE_ANALOG(GPIOC_PIN1) | \ + PIN_MODE_ANALOG(GPIOC_PIN2) | \ + PIN_MODE_ANALOG(GPIOC_PIN3) | \ + PIN_MODE_ANALOG(GPIOC_PIN4) | \ + PIN_MODE_ANALOG(GPIOC_PIN5) | \ + PIN_MODE_ANALOG(GPIOC_PIN6) | \ + PIN_MODE_ANALOG(GPIOC_PIN7) | \ + PIN_MODE_ANALOG(GPIOC_PIN8) | \ + PIN_MODE_ANALOG(GPIOC_PIN9) | \ + PIN_MODE_ANALOG(GPIOC_PIN10) | \ + PIN_MODE_ANALOG(GPIOC_PIN11) | \ + PIN_MODE_ANALOG(GPIOC_PIN12) | \ + PIN_MODE_ANALOG(GPIOC_PIN13) | \ + PIN_MODE_ANALOG(GPIOC_ARD_D7) | \ + PIN_MODE_ANALOG(GPIOC_ARD_D8)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_D8)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ + PIN_OSPEED_HIGH(GPIOC_PIN1) | \ + PIN_OSPEED_HIGH(GPIOC_PIN2) | \ + PIN_OSPEED_HIGH(GPIOC_PIN3) | \ + PIN_OSPEED_HIGH(GPIOC_PIN4) | \ + PIN_OSPEED_HIGH(GPIOC_PIN5) | \ + PIN_OSPEED_HIGH(GPIOC_PIN6) | \ + PIN_OSPEED_HIGH(GPIOC_PIN7) | \ + PIN_OSPEED_HIGH(GPIOC_PIN8) | \ + PIN_OSPEED_HIGH(GPIOC_PIN9) | \ + PIN_OSPEED_HIGH(GPIOC_PIN10) | \ + PIN_OSPEED_HIGH(GPIOC_PIN11) | \ + PIN_OSPEED_HIGH(GPIOC_PIN12) | \ + PIN_OSPEED_HIGH(GPIOC_PIN13) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_D7) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_D8)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOC_ARD_D7) | \ + PIN_PUPDR_FLOATING(GPIOC_ARD_D8)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ + PIN_ODR_HIGH(GPIOC_PIN1) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_PIN7) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_HIGH(GPIOC_PIN10) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_PIN12) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_ARD_D7) | \ + PIN_ODR_HIGH(GPIOC_ARD_D8)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN7, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_D7, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_D8, 0U)) +#define VAL_GPIOC_ASCR (PIN_ASCR_DISABLED(GPIOC_PIN0) | \ + PIN_ASCR_DISABLED(GPIOC_PIN1) | \ + PIN_ASCR_DISABLED(GPIOC_PIN2) | \ + PIN_ASCR_DISABLED(GPIOC_PIN3) | \ + PIN_ASCR_DISABLED(GPIOC_PIN4) | \ + PIN_ASCR_DISABLED(GPIOC_PIN5) | \ + PIN_ASCR_DISABLED(GPIOC_PIN6) | \ + PIN_ASCR_DISABLED(GPIOC_PIN7) | \ + PIN_ASCR_DISABLED(GPIOC_PIN8) | \ + PIN_ASCR_DISABLED(GPIOC_PIN9) | \ + PIN_ASCR_DISABLED(GPIOC_PIN10) | \ + PIN_ASCR_DISABLED(GPIOC_PIN11) | \ + PIN_ASCR_DISABLED(GPIOC_PIN12) | \ + PIN_ASCR_DISABLED(GPIOC_PIN13) | \ + PIN_ASCR_DISABLED(GPIOC_ARD_D7) | \ + PIN_ASCR_DISABLED(GPIOC_ARD_D8)) +#define VAL_GPIOC_LOCKR (PIN_LOCKR_DISABLED(GPIOC_PIN0) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOC_ARD_D7) | \ + PIN_LOCKR_DISABLED(GPIOC_ARD_D8)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (analog). + * PD1 - PIN1 (analog). + * PD2 - PIN2 (analog). + * PD3 - PIN3 (analog). + * PD4 - PIN4 (analog). + * PD5 - PIN5 (analog). + * PD6 - PIN6 (analog). + * PD7 - PIN7 (analog). + * PD8 - PIN8 (analog). + * PD9 - PIN9 (analog). + * PD10 - PIN10 (analog). + * PD11 - PIN11 (analog). + * PD12 - PIN12 (analog). + * PD13 - PIN13 (analog). + * PD14 - PIN14 (analog). + * PD15 - PIN15 (analog). + */ +#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \ + PIN_MODE_ANALOG(GPIOD_PIN1) | \ + PIN_MODE_ANALOG(GPIOD_PIN2) | \ + PIN_MODE_ANALOG(GPIOD_PIN3) | \ + PIN_MODE_ANALOG(GPIOD_PIN4) | \ + PIN_MODE_ANALOG(GPIOD_PIN5) | \ + PIN_MODE_ANALOG(GPIOD_PIN6) | \ + PIN_MODE_ANALOG(GPIOD_PIN7) | \ + PIN_MODE_ANALOG(GPIOD_PIN8) | \ + PIN_MODE_ANALOG(GPIOD_PIN9) | \ + PIN_MODE_ANALOG(GPIOD_PIN10) | \ + PIN_MODE_ANALOG(GPIOD_PIN11) | \ + PIN_MODE_ANALOG(GPIOD_PIN12) | \ + PIN_MODE_ANALOG(GPIOD_PIN13) | \ + PIN_MODE_ANALOG(GPIOD_PIN14) | \ + PIN_MODE_ANALOG(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ + PIN_OSPEED_HIGH(GPIOD_PIN1) | \ + PIN_OSPEED_HIGH(GPIOD_PIN2) | \ + PIN_OSPEED_HIGH(GPIOD_PIN3) | \ + PIN_OSPEED_HIGH(GPIOD_PIN4) | \ + PIN_OSPEED_HIGH(GPIOD_PIN5) | \ + PIN_OSPEED_HIGH(GPIOD_PIN6) | \ + PIN_OSPEED_HIGH(GPIOD_PIN7) | \ + PIN_OSPEED_HIGH(GPIOD_PIN8) | \ + PIN_OSPEED_HIGH(GPIOD_PIN9) | \ + PIN_OSPEED_HIGH(GPIOD_PIN10) | \ + PIN_OSPEED_HIGH(GPIOD_PIN11) | \ + PIN_OSPEED_HIGH(GPIOD_PIN12) | \ + PIN_OSPEED_HIGH(GPIOD_PIN13) | \ + PIN_OSPEED_HIGH(GPIOD_PIN14) | \ + PIN_OSPEED_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_HIGH(GPIOD_PIN12) | \ + PIN_ODR_HIGH(GPIOD_PIN13) | \ + PIN_ODR_HIGH(GPIOD_PIN14) | \ + PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN15, 0U)) +#define VAL_GPIOD_ASCR (PIN_ASCR_DISABLED(GPIOD_PIN0) | \ + PIN_ASCR_DISABLED(GPIOD_PIN1) | \ + PIN_ASCR_DISABLED(GPIOD_PIN2) | \ + PIN_ASCR_DISABLED(GPIOD_PIN3) | \ + PIN_ASCR_DISABLED(GPIOD_PIN4) | \ + PIN_ASCR_DISABLED(GPIOD_PIN5) | \ + PIN_ASCR_DISABLED(GPIOD_PIN6) | \ + PIN_ASCR_DISABLED(GPIOD_PIN7) | \ + PIN_ASCR_DISABLED(GPIOD_PIN8) | \ + PIN_ASCR_DISABLED(GPIOD_PIN9) | \ + PIN_ASCR_DISABLED(GPIOD_PIN10) | \ + PIN_ASCR_DISABLED(GPIOD_PIN11) | \ + PIN_ASCR_DISABLED(GPIOD_PIN12) | \ + PIN_ASCR_DISABLED(GPIOD_PIN13) | \ + PIN_ASCR_DISABLED(GPIOD_PIN14) | \ + PIN_ASCR_DISABLED(GPIOD_PIN15)) +#define VAL_GPIOD_LOCKR (PIN_LOCKR_DISABLED(GPIOD_PIN0) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN15)) + +/* + * GPIOE setup: + * + * PE0 - PIN0 (analog). + * PE1 - PIN1 (analog). + * PE2 - PIN2 (analog). + * PE3 - PIN3 (analog). + * PE4 - PIN4 (analog). + * PE5 - PIN5 (analog). + * PE6 - PIN6 (analog). + * PE7 - PIN7 (analog). + * PE8 - PIN8 (analog). + * PE9 - PIN9 (analog). + * PE10 - PIN10 (analog). + * PE11 - PIN11 (analog). + * PE12 - PIN12 (analog). + * PE13 - PIN13 (analog). + * PE14 - PIN14 (analog). + * PE15 - PIN15 (analog). + */ +#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \ + PIN_MODE_ANALOG(GPIOE_PIN1) | \ + PIN_MODE_ANALOG(GPIOE_PIN2) | \ + PIN_MODE_ANALOG(GPIOE_PIN3) | \ + PIN_MODE_ANALOG(GPIOE_PIN4) | \ + PIN_MODE_ANALOG(GPIOE_PIN5) | \ + PIN_MODE_ANALOG(GPIOE_PIN6) | \ + PIN_MODE_ANALOG(GPIOE_PIN7) | \ + PIN_MODE_ANALOG(GPIOE_PIN8) | \ + PIN_MODE_ANALOG(GPIOE_PIN9) | \ + PIN_MODE_ANALOG(GPIOE_PIN10) | \ + PIN_MODE_ANALOG(GPIOE_PIN11) | \ + PIN_MODE_ANALOG(GPIOE_PIN12) | \ + PIN_MODE_ANALOG(GPIOE_PIN13) | \ + PIN_MODE_ANALOG(GPIOE_PIN14) | \ + PIN_MODE_ANALOG(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ + PIN_OSPEED_HIGH(GPIOE_PIN1) | \ + PIN_OSPEED_HIGH(GPIOE_PIN2) | \ + PIN_OSPEED_HIGH(GPIOE_PIN3) | \ + PIN_OSPEED_HIGH(GPIOE_PIN4) | \ + PIN_OSPEED_HIGH(GPIOE_PIN5) | \ + PIN_OSPEED_HIGH(GPIOE_PIN6) | \ + PIN_OSPEED_HIGH(GPIOE_PIN7) | \ + PIN_OSPEED_HIGH(GPIOE_PIN8) | \ + PIN_OSPEED_HIGH(GPIOE_PIN9) | \ + PIN_OSPEED_HIGH(GPIOE_PIN10) | \ + PIN_OSPEED_HIGH(GPIOE_PIN11) | \ + PIN_OSPEED_HIGH(GPIOE_PIN12) | \ + PIN_OSPEED_HIGH(GPIOE_PIN13) | \ + PIN_OSPEED_HIGH(GPIOE_PIN14) | \ + PIN_OSPEED_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0U)) +#define VAL_GPIOE_ASCR (PIN_ASCR_DISABLED(GPIOE_PIN0) | \ + PIN_ASCR_DISABLED(GPIOE_PIN1) | \ + PIN_ASCR_DISABLED(GPIOE_PIN2) | \ + PIN_ASCR_DISABLED(GPIOE_PIN3) | \ + PIN_ASCR_DISABLED(GPIOE_PIN4) | \ + PIN_ASCR_DISABLED(GPIOE_PIN5) | \ + PIN_ASCR_DISABLED(GPIOE_PIN6) | \ + PIN_ASCR_DISABLED(GPIOE_PIN7) | \ + PIN_ASCR_DISABLED(GPIOE_PIN8) | \ + PIN_ASCR_DISABLED(GPIOE_PIN9) | \ + PIN_ASCR_DISABLED(GPIOE_PIN10) | \ + PIN_ASCR_DISABLED(GPIOE_PIN11) | \ + PIN_ASCR_DISABLED(GPIOE_PIN12) | \ + PIN_ASCR_DISABLED(GPIOE_PIN13) | \ + PIN_ASCR_DISABLED(GPIOE_PIN14) | \ + PIN_ASCR_DISABLED(GPIOE_PIN15)) +#define VAL_GPIOE_LOCKR (PIN_LOCKR_DISABLED(GPIOE_PIN0) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN15)) + +/* + * GPIOF setup: + * + * PF0 - PIN0 (analog). + * PF1 - PIN1 (analog). + * PF2 - PIN2 (analog). + * PF3 - PIN3 (analog). + * PF4 - PIN4 (analog). + * PF5 - PIN5 (analog). + * PF6 - PIN6 (analog). + * PF7 - PIN7 (analog). + * PF8 - PIN8 (analog). + * PF9 - PIN9 (analog). + * PF10 - PIN10 (analog). + * PF11 - PIN11 (analog). + * PF12 - PIN12 (analog). + * PF13 - PIN13 (analog). + * PF14 - PIN14 (analog). + * PF15 - PIN15 (analog). + */ +#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_PIN0) | \ + PIN_MODE_ANALOG(GPIOF_PIN1) | \ + PIN_MODE_ANALOG(GPIOF_PIN2) | \ + PIN_MODE_ANALOG(GPIOF_PIN3) | \ + PIN_MODE_ANALOG(GPIOF_PIN4) | \ + PIN_MODE_ANALOG(GPIOF_PIN5) | \ + PIN_MODE_ANALOG(GPIOF_PIN6) | \ + PIN_MODE_ANALOG(GPIOF_PIN7) | \ + PIN_MODE_ANALOG(GPIOF_PIN8) | \ + PIN_MODE_ANALOG(GPIOF_PIN9) | \ + PIN_MODE_ANALOG(GPIOF_PIN10) | \ + PIN_MODE_ANALOG(GPIOF_PIN11) | \ + PIN_MODE_ANALOG(GPIOF_PIN12) | \ + PIN_MODE_ANALOG(GPIOF_PIN13) | \ + PIN_MODE_ANALOG(GPIOF_PIN14) | \ + PIN_MODE_ANALOG(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ + PIN_OSPEED_HIGH(GPIOF_PIN1) | \ + PIN_OSPEED_HIGH(GPIOF_PIN2) | \ + PIN_OSPEED_HIGH(GPIOF_PIN3) | \ + PIN_OSPEED_HIGH(GPIOF_PIN4) | \ + PIN_OSPEED_HIGH(GPIOF_PIN5) | \ + PIN_OSPEED_HIGH(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_PIN7) | \ + PIN_OSPEED_HIGH(GPIOF_PIN8) | \ + PIN_OSPEED_HIGH(GPIOF_PIN9) | \ + PIN_OSPEED_HIGH(GPIOF_PIN10) | \ + PIN_OSPEED_HIGH(GPIOF_PIN11) | \ + PIN_OSPEED_HIGH(GPIOF_PIN12) | \ + PIN_OSPEED_HIGH(GPIOF_PIN13) | \ + PIN_OSPEED_HIGH(GPIOF_PIN14) | \ + PIN_OSPEED_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0U)) +#define VAL_GPIOF_ASCR (PIN_ASCR_DISABLED(GPIOF_PIN0) | \ + PIN_ASCR_DISABLED(GPIOF_PIN1) | \ + PIN_ASCR_DISABLED(GPIOF_PIN2) | \ + PIN_ASCR_DISABLED(GPIOF_PIN3) | \ + PIN_ASCR_DISABLED(GPIOF_PIN4) | \ + PIN_ASCR_DISABLED(GPIOF_PIN5) | \ + PIN_ASCR_DISABLED(GPIOF_PIN6) | \ + PIN_ASCR_DISABLED(GPIOF_PIN7) | \ + PIN_ASCR_DISABLED(GPIOF_PIN8) | \ + PIN_ASCR_DISABLED(GPIOF_PIN9) | \ + PIN_ASCR_DISABLED(GPIOF_PIN10) | \ + PIN_ASCR_DISABLED(GPIOF_PIN11) | \ + PIN_ASCR_DISABLED(GPIOF_PIN12) | \ + PIN_ASCR_DISABLED(GPIOF_PIN13) | \ + PIN_ASCR_DISABLED(GPIOF_PIN14) | \ + PIN_ASCR_DISABLED(GPIOF_PIN15)) +#define VAL_GPIOF_LOCKR (PIN_LOCKR_DISABLED(GPIOF_PIN0) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN15)) + +/* + * GPIOG setup: + * + * PG0 - PIN0 (analog). + * PG1 - PIN1 (analog). + * PG2 - PIN2 (analog). + * PG3 - PIN3 (analog). + * PG4 - PIN4 (analog). + * PG5 - PIN5 (analog). + * PG6 - PIN6 (analog). + * PG7 - PIN7 (analog). + * PG8 - PIN8 (analog). + * PG9 - PIN9 (analog). + * PG10 - PIN10 (analog). + * PG11 - PIN11 (analog). + * PG12 - PIN12 (analog). + * PG13 - PIN13 (analog). + * PG14 - PIN14 (analog). + * PG15 - PIN15 (analog). + */ +#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \ + PIN_MODE_ANALOG(GPIOG_PIN1) | \ + PIN_MODE_ANALOG(GPIOG_PIN2) | \ + PIN_MODE_ANALOG(GPIOG_PIN3) | \ + PIN_MODE_ANALOG(GPIOG_PIN4) | \ + PIN_MODE_ANALOG(GPIOG_PIN5) | \ + PIN_MODE_ANALOG(GPIOG_PIN6) | \ + PIN_MODE_ANALOG(GPIOG_PIN7) | \ + PIN_MODE_ANALOG(GPIOG_PIN8) | \ + PIN_MODE_ANALOG(GPIOG_PIN9) | \ + PIN_MODE_ANALOG(GPIOG_PIN10) | \ + PIN_MODE_ANALOG(GPIOG_PIN11) | \ + PIN_MODE_ANALOG(GPIOG_PIN12) | \ + PIN_MODE_ANALOG(GPIOG_PIN13) | \ + PIN_MODE_ANALOG(GPIOG_PIN14) | \ + PIN_MODE_ANALOG(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ + PIN_ODR_HIGH(GPIOG_PIN1) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_PIN6) | \ + PIN_ODR_HIGH(GPIOG_PIN7) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_PIN11) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_PIN13) | \ + PIN_ODR_HIGH(GPIOG_PIN14) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN7, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0U)) +#define VAL_GPIOG_ASCR (PIN_ASCR_DISABLED(GPIOG_PIN0) | \ + PIN_ASCR_DISABLED(GPIOG_PIN1) | \ + PIN_ASCR_DISABLED(GPIOG_PIN2) | \ + PIN_ASCR_DISABLED(GPIOG_PIN3) | \ + PIN_ASCR_DISABLED(GPIOG_PIN4) | \ + PIN_ASCR_DISABLED(GPIOG_PIN5) | \ + PIN_ASCR_DISABLED(GPIOG_PIN6) | \ + PIN_ASCR_DISABLED(GPIOG_PIN7) | \ + PIN_ASCR_DISABLED(GPIOG_PIN8) | \ + PIN_ASCR_DISABLED(GPIOG_PIN9) | \ + PIN_ASCR_DISABLED(GPIOG_PIN10) | \ + PIN_ASCR_DISABLED(GPIOG_PIN11) | \ + PIN_ASCR_DISABLED(GPIOG_PIN12) | \ + PIN_ASCR_DISABLED(GPIOG_PIN13) | \ + PIN_ASCR_DISABLED(GPIOG_PIN14) | \ + PIN_ASCR_DISABLED(GPIOG_PIN15)) +#define VAL_GPIOG_LOCKR (PIN_LOCKR_DISABLED(GPIOG_PIN0) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN15)) + +/* + * GPIOH setup: + * + * PH0 - PIN0 (analog). + * PH1 - PIN1 (analog). + * PH2 - PIN2 (analog). + * PH3 - PIN3 (analog). + * PH4 - PIN4 (analog). + * PH5 - PIN5 (analog). + * PH6 - PIN6 (analog). + * PH7 - PIN7 (analog). + * PH8 - PIN8 (analog). + * PH9 - PIN9 (analog). + * PH10 - PIN10 (analog). + * PH11 - PIN11 (analog). + * PH12 - PIN12 (analog). + * PH13 - PIN13 (analog). + * PH14 - PIN14 (analog). + * PH15 - PIN15 (analog). + */ +#define VAL_GPIOH_MODER (PIN_MODE_ANALOG(GPIOH_PIN0) | \ + PIN_MODE_ANALOG(GPIOH_PIN1) | \ + PIN_MODE_ANALOG(GPIOH_PIN2) | \ + PIN_MODE_ANALOG(GPIOH_PIN3) | \ + PIN_MODE_ANALOG(GPIOH_PIN4) | \ + PIN_MODE_ANALOG(GPIOH_PIN5) | \ + PIN_MODE_ANALOG(GPIOH_PIN6) | \ + PIN_MODE_ANALOG(GPIOH_PIN7) | \ + PIN_MODE_ANALOG(GPIOH_PIN8) | \ + PIN_MODE_ANALOG(GPIOH_PIN9) | \ + PIN_MODE_ANALOG(GPIOH_PIN10) | \ + PIN_MODE_ANALOG(GPIOH_PIN11) | \ + PIN_MODE_ANALOG(GPIOH_PIN12) | \ + PIN_MODE_ANALOG(GPIOH_PIN13) | \ + PIN_MODE_ANALOG(GPIOH_PIN14) | \ + PIN_MODE_ANALOG(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_PIN0) | \ + PIN_OSPEED_HIGH(GPIOH_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_PIN0) | \ + PIN_ODR_HIGH(GPIOH_PIN1) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) +#define VAL_GPIOH_ASCR (PIN_ASCR_DISABLED(GPIOH_PIN0) | \ + PIN_ASCR_DISABLED(GPIOH_PIN1) | \ + PIN_ASCR_DISABLED(GPIOH_PIN2) | \ + PIN_ASCR_DISABLED(GPIOH_PIN3) | \ + PIN_ASCR_DISABLED(GPIOH_PIN4) | \ + PIN_ASCR_DISABLED(GPIOH_PIN5) | \ + PIN_ASCR_DISABLED(GPIOH_PIN6) | \ + PIN_ASCR_DISABLED(GPIOH_PIN7) | \ + PIN_ASCR_DISABLED(GPIOH_PIN8) | \ + PIN_ASCR_DISABLED(GPIOH_PIN9) | \ + PIN_ASCR_DISABLED(GPIOH_PIN10) | \ + PIN_ASCR_DISABLED(GPIOH_PIN11) | \ + PIN_ASCR_DISABLED(GPIOH_PIN12) | \ + PIN_ASCR_DISABLED(GPIOH_PIN13) | \ + PIN_ASCR_DISABLED(GPIOH_PIN14) | \ + PIN_ASCR_DISABLED(GPIOH_PIN15)) +#define VAL_GPIOH_LOCKR (PIN_LOCKR_DISABLED(GPIOH_PIN0) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN15)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/platforms/chibios/GENERIC_STM32_L433XC/board/board.mk b/platforms/chibios/GENERIC_STM32_L433XC/board/board.mk index aaf4ed068c9d..842e33590594 100644 --- a/platforms/chibios/GENERIC_STM32_L433XC/board/board.mk +++ b/platforms/chibios/GENERIC_STM32_L433XC/board/board.mk @@ -1,8 +1,8 @@ # List of all the board related files. -BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC/board.c +BOARDSRC = $(BOARD_PATH)/board/board.c -# Required include directories -BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC +# Required include directories +BOARDINC = $(BOARD_PATH)/board # Shared variables ALLCSRC += $(BOARDSRC) From 68d797dd8604e3341e9384ad2bc12789784bf141 Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Thu, 11 Mar 2021 15:31:56 +1100 Subject: [PATCH 08/24] revert its own board files --- .../GENERIC_STM32_L433XC/board/board.c | 281 ---- .../GENERIC_STM32_L433XC/board/board.h | 1489 +---------------- .../GENERIC_STM32_L433XC/board/board.mk | 4 +- 3 files changed, 5 insertions(+), 1769 deletions(-) delete mode 100644 platforms/chibios/GENERIC_STM32_L433XC/board/board.c diff --git a/platforms/chibios/GENERIC_STM32_L433XC/board/board.c b/platforms/chibios/GENERIC_STM32_L433XC/board/board.c deleted file mode 100644 index fceb3fdec6c3..000000000000 --- a/platforms/chibios/GENERIC_STM32_L433XC/board/board.c +++ /dev/null @@ -1,281 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; - uint32_t ascr; - uint32_t lockr; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR, - VAL_GPIOA_LOCKR}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR, - VAL_GPIOB_LOCKR}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR, - VAL_GPIOC_LOCKR}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR, - VAL_GPIOD_LOCKR}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR, - VAL_GPIOE_LOCKR}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR, - VAL_GPIOF_LOCKR}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR, - VAL_GPIOG_LOCKR}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR, - VAL_GPIOH_LOCKR}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR, - VAL_GPIOI_LOCKR}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR, - VAL_GPIOJ_LOCKR}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR, - VAL_GPIOK_LOCKR} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->ASCR = config->ascr; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; - gpiop->LOCKR = config->lockr; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB2(STM32_GPIO_EN_MASK); - rccEnableAHB2(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* CHTODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* CHTODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* CHTODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* CHTODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @note You can add your board-specific code here. - */ -void boardInit(void) { - -} diff --git a/platforms/chibios/GENERIC_STM32_L433XC/board/board.h b/platforms/chibios/GENERIC_STM32_L433XC/board/board.h index 35d136d088a8..1d7feae20271 100644 --- a/platforms/chibios/GENERIC_STM32_L433XC/board/board.h +++ b/platforms/chibios/GENERIC_STM32_L433XC/board/board.h @@ -1,1486 +1,3 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Setup for STMicroelectronics STM32 Nucleo32-L432KC board. - */ - -/* - * Board identifier. - */ -#define BOARD_GENERIC_STM32_L433XC -#define BOARD_NAME "Generic STM32L433 PCB" - -/* - * Board oscillators-related settings. - * NOTE: HSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 32768U -#endif - -#define STM32_LSEDRV (2U << 3U) - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 0U -#endif - -/* - * Board voltages. - * Required for performance limits calculation. - */ -#define STM32_VDD 300U - -/* - * MCU type as defined in the ST header. - */ -#define STM32L433xx - -/* - * IO pins assignments. - */ -#define GPIOA_ARD_A0 0U -#define GPIOA_ARD_A1 1U -#define GPIOA_VCP_TX 2U -#define GPIOA_ARD_A2 3U -#define GPIOA_ARD_A3 4U -#define GPIOA_ARD_A4 5U -#define GPIOA_ARD_A5 6U -#define GPIOA_ARD_A6 7U -#define GPIOA_ARD_D9 8U -#define GPIOA_ARD_D1 9U -#define GPIOA_ARD_D0 10U -#define GPIOA_ARD_D10 11U -#define GPIOA_ARD_D2 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_VCP_RX 15U - -#define GPIOB_ARD_D3 0U -#define GPIOB_ARD_D6 1U -#define GPIOB_PIN2 2U -#define GPIOB_ARD_D13 3U -#define GPIOB_LED_GREEN 3U -#define GPIOB_ARD_D12 4U -#define GPIOB_ARD_D11 5U -#define GPIOB_ARD_D5 6U -#define GPIOB_ARD_A5_ALT 6U -#define GPIOB_ARD_D4 7U -#define GPIOB_ARD_A4_ALT 7U -#define GPIOB_PIN8 8U -#define GPIOB_PIN9 9U -#define GPIOB_PIN10 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_PIN13 13U -#define GPIOB_PIN14 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_ARD_D7 14U -#define GPIOC_ARD_D8 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_PIN0 0U -#define GPIOF_PIN1 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_PIN6 6U -#define GPIOG_PIN7 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_PIN11 11U -#define GPIOG_PIN12 12U -#define GPIOG_PIN13 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_PIN0 0U -#define GPIOH_PIN1 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U) -#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U) -#define LINE_VCP_TX PAL_LINE(GPIOA, 2U) -#define LINE_ARD_A2 PAL_LINE(GPIOA, 3U) -#define LINE_ARD_A3 PAL_LINE(GPIOA, 4U) -#define LINE_ARD_A4 PAL_LINE(GPIOA, 5U) -#define LINE_ARD_A5 PAL_LINE(GPIOA, 6U) -#define LINE_ARD_A6 PAL_LINE(GPIOA, 7U) -#define LINE_ARD_D9 PAL_LINE(GPIOA, 8U) -#define LINE_ARD_D1 PAL_LINE(GPIOA, 9U) -#define LINE_ARD_D0 PAL_LINE(GPIOA, 10U) -#define LINE_ARD_D10 PAL_LINE(GPIOA, 11U) -#define LINE_ARD_D2 PAL_LINE(GPIOA, 12U) -#define LINE_SWDIO PAL_LINE(GPIOA, 13U) -#define LINE_SWCLK PAL_LINE(GPIOA, 14U) -#define LINE_VCP_RX PAL_LINE(GPIOA, 15U) -#define LINE_ARD_D3 PAL_LINE(GPIOB, 0U) -#define LINE_ARD_D6 PAL_LINE(GPIOB, 1U) -#define LINE_ARD_D13 PAL_LINE(GPIOB, 3U) -#define LINE_LED_GREEN PAL_LINE(GPIOB, 3U) -#define LINE_ARD_D12 PAL_LINE(GPIOB, 4U) -#define LINE_ARD_D11 PAL_LINE(GPIOB, 5U) -#define LINE_ARD_D5 PAL_LINE(GPIOB, 6U) -#define LINE_ARD_A5_ALT PAL_LINE(GPIOB, 6U) -#define LINE_ARD_D4 PAL_LINE(GPIOB, 7U) -#define LINE_ARD_A4_ALT PAL_LINE(GPIOB, 7U) -#define LINE_ARD_D7 PAL_LINE(GPIOC, 14U) -#define LINE_ARD_D8 PAL_LINE(GPIOC, 15U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) -#define PIN_ASCR_DISABLED(n) (0U << (n)) -#define PIN_ASCR_ENABLED(n) (1U << (n)) -#define PIN_LOCKR_DISABLED(n) (0U << (n)) -#define PIN_LOCKR_ENABLED(n) (1U << (n)) - -/* - * GPIOA setup: - * - * PA0 - ARD_A0 (analog). - * PA1 - ARD_A1 (analog). - * PA2 - VCP_TX (alternate 7). - * PA3 - ARD_A2 (analog). - * PA4 - ARD_A3 (analog). - * PA5 - ARD_A4 (analog). - * PA6 - ARD_A5 (analog). - * PA7 - ARD_A6 (analog). - * PA8 - ARD_D9 (analog). - * PA9 - ARD_D1 (analog). - * PA10 - ARD_D0 (analog). - * PA11 - ARD_D10 (analog). - * PA12 - ARD_D2 (analog). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - VCP_RX (alternate 3). - */ -#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_ARD_A0) | \ - PIN_MODE_ANALOG(GPIOA_ARD_A1) | \ - PIN_MODE_ALTERNATE(GPIOA_VCP_TX) | \ - PIN_MODE_ANALOG(GPIOA_ARD_A2) | \ - PIN_MODE_ANALOG(GPIOA_ARD_A3) | \ - PIN_MODE_ANALOG(GPIOA_ARD_A4) | \ - PIN_MODE_ANALOG(GPIOA_ARD_A5) | \ - PIN_MODE_ANALOG(GPIOA_ARD_A6) | \ - PIN_MODE_ANALOG(GPIOA_ARD_D9) | \ - PIN_MODE_ANALOG(GPIOA_ARD_D1) | \ - PIN_MODE_ANALOG(GPIOA_ARD_D0) | \ - PIN_MODE_ANALOG(GPIOA_ARD_D10) | \ - PIN_MODE_ANALOG(GPIOA_ARD_D2) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_ALTERNATE(GPIOA_VCP_RX)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_VCP_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_A3) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_A4) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_A5) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_A6) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_D9) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_D10) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_VCP_RX)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \ - PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \ - PIN_OSPEED_MEDIUM(GPIOA_VCP_TX) | \ - PIN_OSPEED_MEDIUM(GPIOA_ARD_A2) | \ - PIN_OSPEED_HIGH(GPIOA_ARD_A3) | \ - PIN_OSPEED_HIGH(GPIOA_ARD_A4) | \ - PIN_OSPEED_HIGH(GPIOA_ARD_A5) | \ - PIN_OSPEED_HIGH(GPIOA_ARD_A6) | \ - PIN_OSPEED_HIGH(GPIOA_ARD_D9) | \ - PIN_OSPEED_HIGH(GPIOA_ARD_D1) | \ - PIN_OSPEED_HIGH(GPIOA_ARD_D0) | \ - PIN_OSPEED_HIGH(GPIOA_ARD_D10) | \ - PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_VCP_RX)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_ARD_A0) | \ - PIN_PUPDR_FLOATING(GPIOA_ARD_A1) | \ - PIN_PUPDR_FLOATING(GPIOA_VCP_TX) | \ - PIN_PUPDR_FLOATING(GPIOA_ARD_A2) | \ - PIN_PUPDR_FLOATING(GPIOA_ARD_A3) | \ - PIN_PUPDR_FLOATING(GPIOA_ARD_A4) | \ - PIN_PUPDR_FLOATING(GPIOA_ARD_A5) | \ - PIN_PUPDR_FLOATING(GPIOA_ARD_A6) | \ - PIN_PUPDR_FLOATING(GPIOA_ARD_D9) | \ - PIN_PUPDR_FLOATING(GPIOA_ARD_D1) | \ - PIN_PUPDR_FLOATING(GPIOA_ARD_D0) | \ - PIN_PUPDR_FLOATING(GPIOA_ARD_D10) | \ - PIN_PUPDR_FLOATING(GPIOA_ARD_D2) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_FLOATING(GPIOA_VCP_RX)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \ - PIN_ODR_HIGH(GPIOA_ARD_A1) | \ - PIN_ODR_HIGH(GPIOA_VCP_TX) | \ - PIN_ODR_HIGH(GPIOA_ARD_A2) | \ - PIN_ODR_HIGH(GPIOA_ARD_A3) | \ - PIN_ODR_HIGH(GPIOA_ARD_A4) | \ - PIN_ODR_HIGH(GPIOA_ARD_A5) | \ - PIN_ODR_HIGH(GPIOA_ARD_A6) | \ - PIN_ODR_HIGH(GPIOA_ARD_D9) | \ - PIN_ODR_HIGH(GPIOA_ARD_D1) | \ - PIN_ODR_HIGH(GPIOA_ARD_D0) | \ - PIN_ODR_HIGH(GPIOA_ARD_D10) | \ - PIN_ODR_HIGH(GPIOA_ARD_D2) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_VCP_RX)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \ - PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \ - PIN_AFIO_AF(GPIOA_VCP_TX, 7U) | \ - PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \ - PIN_AFIO_AF(GPIOA_ARD_A3, 0U) | \ - PIN_AFIO_AF(GPIOA_ARD_A4, 0U) | \ - PIN_AFIO_AF(GPIOA_ARD_A5, 0U) | \ - PIN_AFIO_AF(GPIOA_ARD_A6, 0U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D9, 0U) | \ - PIN_AFIO_AF(GPIOA_ARD_D1, 0U) | \ - PIN_AFIO_AF(GPIOA_ARD_D0, 0U) | \ - PIN_AFIO_AF(GPIOA_ARD_D10, 0U) | \ - PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_VCP_RX, 3U)) -#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_ARD_A0) | \ - PIN_ASCR_DISABLED(GPIOA_ARD_A1) | \ - PIN_ASCR_DISABLED(GPIOA_VCP_TX) | \ - PIN_ASCR_DISABLED(GPIOA_ARD_A2) | \ - PIN_ASCR_DISABLED(GPIOA_ARD_A3) | \ - PIN_ASCR_DISABLED(GPIOA_ARD_A4) | \ - PIN_ASCR_DISABLED(GPIOA_ARD_A5) | \ - PIN_ASCR_DISABLED(GPIOA_ARD_A6) | \ - PIN_ASCR_DISABLED(GPIOA_ARD_D9) | \ - PIN_ASCR_DISABLED(GPIOA_ARD_D1) | \ - PIN_ASCR_DISABLED(GPIOA_ARD_D0) | \ - PIN_ASCR_DISABLED(GPIOA_ARD_D10) | \ - PIN_ASCR_DISABLED(GPIOA_ARD_D2) | \ - PIN_ASCR_DISABLED(GPIOA_SWDIO) | \ - PIN_ASCR_DISABLED(GPIOA_SWCLK) | \ - PIN_ASCR_DISABLED(GPIOA_VCP_RX)) -#define VAL_GPIOA_LOCKR (PIN_LOCKR_DISABLED(GPIOA_ARD_A0) | \ - PIN_LOCKR_DISABLED(GPIOA_ARD_A1) | \ - PIN_LOCKR_DISABLED(GPIOA_VCP_TX) | \ - PIN_LOCKR_DISABLED(GPIOA_ARD_A2) | \ - PIN_LOCKR_DISABLED(GPIOA_ARD_A3) | \ - PIN_LOCKR_DISABLED(GPIOA_ARD_A4) | \ - PIN_LOCKR_DISABLED(GPIOA_ARD_A5) | \ - PIN_LOCKR_DISABLED(GPIOA_ARD_A6) | \ - PIN_LOCKR_DISABLED(GPIOA_ARD_D9) | \ - PIN_LOCKR_DISABLED(GPIOA_ARD_D1) | \ - PIN_LOCKR_DISABLED(GPIOA_ARD_D0) | \ - PIN_LOCKR_DISABLED(GPIOA_ARD_D10) | \ - PIN_LOCKR_DISABLED(GPIOA_ARD_D2) | \ - PIN_LOCKR_DISABLED(GPIOA_SWDIO) | \ - PIN_LOCKR_DISABLED(GPIOA_SWCLK) | \ - PIN_LOCKR_DISABLED(GPIOA_VCP_RX)) - -/* - * GPIOB setup: - * - * PB0 - ARD_D3 (input pullup). - * PB1 - ARD_D6 (analog). - * PB2 - PIN2 (analog). - * PB3 - ARD_D13 LED_GREEN (output pushpull maximum). - * PB4 - ARD_D12 (analog). - * PB5 - ARD_D11 (analog). - * PB6 - ARD_D5 ARD_A5_ALT (analog). - * PB7 - ARD_D4 ARD_A4_ALT (analog). - * PB8 - PIN8 (analog). - * PB9 - PIN9 (analog). - * PB10 - PIN10 (analog). - * PB11 - PIN11 (analog). - * PB12 - PIN12 (analog). - * PB13 - PIN13 (analog). - * PB14 - PIN14 (analog). - * PB15 - PIN15 (analog). - */ -#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_ARD_D3) | \ - PIN_MODE_ANALOG(GPIOB_ARD_D6) | \ - PIN_MODE_ANALOG(GPIOB_PIN2) | \ - PIN_MODE_OUTPUT(GPIOB_ARD_D13) | \ - PIN_MODE_ANALOG(GPIOB_ARD_D12) | \ - PIN_MODE_ANALOG(GPIOB_ARD_D11) | \ - PIN_MODE_ANALOG(GPIOB_ARD_D5) | \ - PIN_MODE_ANALOG(GPIOB_ARD_D4) | \ - PIN_MODE_ANALOG(GPIOB_PIN8) | \ - PIN_MODE_ANALOG(GPIOB_PIN9) | \ - PIN_MODE_ANALOG(GPIOB_PIN10) | \ - PIN_MODE_ANALOG(GPIOB_PIN11) | \ - PIN_MODE_ANALOG(GPIOB_PIN12) | \ - PIN_MODE_ANALOG(GPIOB_PIN13) | \ - PIN_MODE_ANALOG(GPIOB_PIN14) | \ - PIN_MODE_ANALOG(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ARD_D3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ARD_D13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ARD_D12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ARD_D11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ARD_D3) | \ - PIN_OSPEED_HIGH(GPIOB_ARD_D6) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_ARD_D13) | \ - PIN_OSPEED_HIGH(GPIOB_ARD_D12) | \ - PIN_OSPEED_HIGH(GPIOB_ARD_D11) | \ - PIN_OSPEED_HIGH(GPIOB_ARD_D5) | \ - PIN_OSPEED_HIGH(GPIOB_ARD_D4) | \ - PIN_OSPEED_HIGH(GPIOB_PIN8) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_PIN10) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_PIN13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN14) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_ARD_D3) | \ - PIN_PUPDR_FLOATING(GPIOB_ARD_D6) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOB_ARD_D13) | \ - PIN_PUPDR_FLOATING(GPIOB_ARD_D12) | \ - PIN_PUPDR_FLOATING(GPIOB_ARD_D11) | \ - PIN_PUPDR_FLOATING(GPIOB_ARD_D5) | \ - PIN_PUPDR_FLOATING(GPIOB_ARD_D4) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ARD_D3) | \ - PIN_ODR_HIGH(GPIOB_ARD_D6) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_LOW(GPIOB_ARD_D13) | \ - PIN_ODR_HIGH(GPIOB_ARD_D12) | \ - PIN_ODR_HIGH(GPIOB_ARD_D11) | \ - PIN_ODR_HIGH(GPIOB_ARD_D5) | \ - PIN_ODR_HIGH(GPIOB_ARD_D4) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_PIN14) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_D3, 0U) | \ - PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_ARD_D13, 0U) | \ - PIN_AFIO_AF(GPIOB_ARD_D12, 0U) | \ - PIN_AFIO_AF(GPIOB_ARD_D11, 0U) | \ - PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \ - PIN_AFIO_AF(GPIOB_ARD_D4, 0U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) -#define VAL_GPIOB_ASCR (PIN_ASCR_DISABLED(GPIOB_ARD_D3) | \ - PIN_ASCR_DISABLED(GPIOB_ARD_D6) | \ - PIN_ASCR_DISABLED(GPIOB_PIN2) | \ - PIN_ASCR_DISABLED(GPIOB_ARD_D13) | \ - PIN_ASCR_DISABLED(GPIOB_ARD_D12) | \ - PIN_ASCR_DISABLED(GPIOB_ARD_D11) | \ - PIN_ASCR_DISABLED(GPIOB_ARD_D5) | \ - PIN_ASCR_DISABLED(GPIOB_ARD_D4) | \ - PIN_ASCR_DISABLED(GPIOB_PIN8) | \ - PIN_ASCR_DISABLED(GPIOB_PIN9) | \ - PIN_ASCR_DISABLED(GPIOB_PIN10) | \ - PIN_ASCR_DISABLED(GPIOB_PIN11) | \ - PIN_ASCR_DISABLED(GPIOB_PIN12) | \ - PIN_ASCR_DISABLED(GPIOB_PIN13) | \ - PIN_ASCR_DISABLED(GPIOB_PIN14) | \ - PIN_ASCR_DISABLED(GPIOB_PIN15)) -#define VAL_GPIOB_LOCKR (PIN_LOCKR_DISABLED(GPIOB_ARD_D3) | \ - PIN_LOCKR_DISABLED(GPIOB_ARD_D6) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOB_ARD_D13) | \ - PIN_LOCKR_DISABLED(GPIOB_ARD_D12) | \ - PIN_LOCKR_DISABLED(GPIOB_ARD_D11) | \ - PIN_LOCKR_DISABLED(GPIOB_ARD_D5) | \ - PIN_LOCKR_DISABLED(GPIOB_ARD_D4) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN15)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (analog). - * PC1 - PIN1 (analog). - * PC2 - PIN2 (analog). - * PC3 - PIN3 (analog). - * PC4 - PIN4 (analog). - * PC5 - PIN5 (analog). - * PC6 - PIN6 (analog). - * PC7 - PIN7 (analog). - * PC8 - PIN8 (analog). - * PC9 - PIN9 (analog). - * PC10 - PIN10 (analog). - * PC11 - PIN11 (analog). - * PC12 - PIN12 (analog). - * PC13 - PIN13 (analog). - * PC14 - ARD_D7 (analog). - * PC15 - ARD_D8 (analog). - */ -#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_PIN0) | \ - PIN_MODE_ANALOG(GPIOC_PIN1) | \ - PIN_MODE_ANALOG(GPIOC_PIN2) | \ - PIN_MODE_ANALOG(GPIOC_PIN3) | \ - PIN_MODE_ANALOG(GPIOC_PIN4) | \ - PIN_MODE_ANALOG(GPIOC_PIN5) | \ - PIN_MODE_ANALOG(GPIOC_PIN6) | \ - PIN_MODE_ANALOG(GPIOC_PIN7) | \ - PIN_MODE_ANALOG(GPIOC_PIN8) | \ - PIN_MODE_ANALOG(GPIOC_PIN9) | \ - PIN_MODE_ANALOG(GPIOC_PIN10) | \ - PIN_MODE_ANALOG(GPIOC_PIN11) | \ - PIN_MODE_ANALOG(GPIOC_PIN12) | \ - PIN_MODE_ANALOG(GPIOC_PIN13) | \ - PIN_MODE_ANALOG(GPIOC_ARD_D7) | \ - PIN_MODE_ANALOG(GPIOC_ARD_D8)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_ARD_D7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_ARD_D8)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_ARD_D7) | \ - PIN_OSPEED_HIGH(GPIOC_ARD_D8)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_ARD_D7) | \ - PIN_PUPDR_FLOATING(GPIOC_ARD_D8)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_ARD_D7) | \ - PIN_ODR_HIGH(GPIOC_ARD_D8)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_ARD_D7, 0U) | \ - PIN_AFIO_AF(GPIOC_ARD_D8, 0U)) -#define VAL_GPIOC_ASCR (PIN_ASCR_DISABLED(GPIOC_PIN0) | \ - PIN_ASCR_DISABLED(GPIOC_PIN1) | \ - PIN_ASCR_DISABLED(GPIOC_PIN2) | \ - PIN_ASCR_DISABLED(GPIOC_PIN3) | \ - PIN_ASCR_DISABLED(GPIOC_PIN4) | \ - PIN_ASCR_DISABLED(GPIOC_PIN5) | \ - PIN_ASCR_DISABLED(GPIOC_PIN6) | \ - PIN_ASCR_DISABLED(GPIOC_PIN7) | \ - PIN_ASCR_DISABLED(GPIOC_PIN8) | \ - PIN_ASCR_DISABLED(GPIOC_PIN9) | \ - PIN_ASCR_DISABLED(GPIOC_PIN10) | \ - PIN_ASCR_DISABLED(GPIOC_PIN11) | \ - PIN_ASCR_DISABLED(GPIOC_PIN12) | \ - PIN_ASCR_DISABLED(GPIOC_PIN13) | \ - PIN_ASCR_DISABLED(GPIOC_ARD_D7) | \ - PIN_ASCR_DISABLED(GPIOC_ARD_D8)) -#define VAL_GPIOC_LOCKR (PIN_LOCKR_DISABLED(GPIOC_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOC_ARD_D7) | \ - PIN_LOCKR_DISABLED(GPIOC_ARD_D8)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (analog). - * PD1 - PIN1 (analog). - * PD2 - PIN2 (analog). - * PD3 - PIN3 (analog). - * PD4 - PIN4 (analog). - * PD5 - PIN5 (analog). - * PD6 - PIN6 (analog). - * PD7 - PIN7 (analog). - * PD8 - PIN8 (analog). - * PD9 - PIN9 (analog). - * PD10 - PIN10 (analog). - * PD11 - PIN11 (analog). - * PD12 - PIN12 (analog). - * PD13 - PIN13 (analog). - * PD14 - PIN14 (analog). - * PD15 - PIN15 (analog). - */ -#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \ - PIN_MODE_ANALOG(GPIOD_PIN1) | \ - PIN_MODE_ANALOG(GPIOD_PIN2) | \ - PIN_MODE_ANALOG(GPIOD_PIN3) | \ - PIN_MODE_ANALOG(GPIOD_PIN4) | \ - PIN_MODE_ANALOG(GPIOD_PIN5) | \ - PIN_MODE_ANALOG(GPIOD_PIN6) | \ - PIN_MODE_ANALOG(GPIOD_PIN7) | \ - PIN_MODE_ANALOG(GPIOD_PIN8) | \ - PIN_MODE_ANALOG(GPIOD_PIN9) | \ - PIN_MODE_ANALOG(GPIOD_PIN10) | \ - PIN_MODE_ANALOG(GPIOD_PIN11) | \ - PIN_MODE_ANALOG(GPIOD_PIN12) | \ - PIN_MODE_ANALOG(GPIOD_PIN13) | \ - PIN_MODE_ANALOG(GPIOD_PIN14) | \ - PIN_MODE_ANALOG(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) -#define VAL_GPIOD_ASCR (PIN_ASCR_DISABLED(GPIOD_PIN0) | \ - PIN_ASCR_DISABLED(GPIOD_PIN1) | \ - PIN_ASCR_DISABLED(GPIOD_PIN2) | \ - PIN_ASCR_DISABLED(GPIOD_PIN3) | \ - PIN_ASCR_DISABLED(GPIOD_PIN4) | \ - PIN_ASCR_DISABLED(GPIOD_PIN5) | \ - PIN_ASCR_DISABLED(GPIOD_PIN6) | \ - PIN_ASCR_DISABLED(GPIOD_PIN7) | \ - PIN_ASCR_DISABLED(GPIOD_PIN8) | \ - PIN_ASCR_DISABLED(GPIOD_PIN9) | \ - PIN_ASCR_DISABLED(GPIOD_PIN10) | \ - PIN_ASCR_DISABLED(GPIOD_PIN11) | \ - PIN_ASCR_DISABLED(GPIOD_PIN12) | \ - PIN_ASCR_DISABLED(GPIOD_PIN13) | \ - PIN_ASCR_DISABLED(GPIOD_PIN14) | \ - PIN_ASCR_DISABLED(GPIOD_PIN15)) -#define VAL_GPIOD_LOCKR (PIN_LOCKR_DISABLED(GPIOD_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN15)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (analog). - * PE1 - PIN1 (analog). - * PE2 - PIN2 (analog). - * PE3 - PIN3 (analog). - * PE4 - PIN4 (analog). - * PE5 - PIN5 (analog). - * PE6 - PIN6 (analog). - * PE7 - PIN7 (analog). - * PE8 - PIN8 (analog). - * PE9 - PIN9 (analog). - * PE10 - PIN10 (analog). - * PE11 - PIN11 (analog). - * PE12 - PIN12 (analog). - * PE13 - PIN13 (analog). - * PE14 - PIN14 (analog). - * PE15 - PIN15 (analog). - */ -#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \ - PIN_MODE_ANALOG(GPIOE_PIN1) | \ - PIN_MODE_ANALOG(GPIOE_PIN2) | \ - PIN_MODE_ANALOG(GPIOE_PIN3) | \ - PIN_MODE_ANALOG(GPIOE_PIN4) | \ - PIN_MODE_ANALOG(GPIOE_PIN5) | \ - PIN_MODE_ANALOG(GPIOE_PIN6) | \ - PIN_MODE_ANALOG(GPIOE_PIN7) | \ - PIN_MODE_ANALOG(GPIOE_PIN8) | \ - PIN_MODE_ANALOG(GPIOE_PIN9) | \ - PIN_MODE_ANALOG(GPIOE_PIN10) | \ - PIN_MODE_ANALOG(GPIOE_PIN11) | \ - PIN_MODE_ANALOG(GPIOE_PIN12) | \ - PIN_MODE_ANALOG(GPIOE_PIN13) | \ - PIN_MODE_ANALOG(GPIOE_PIN14) | \ - PIN_MODE_ANALOG(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) -#define VAL_GPIOE_ASCR (PIN_ASCR_DISABLED(GPIOE_PIN0) | \ - PIN_ASCR_DISABLED(GPIOE_PIN1) | \ - PIN_ASCR_DISABLED(GPIOE_PIN2) | \ - PIN_ASCR_DISABLED(GPIOE_PIN3) | \ - PIN_ASCR_DISABLED(GPIOE_PIN4) | \ - PIN_ASCR_DISABLED(GPIOE_PIN5) | \ - PIN_ASCR_DISABLED(GPIOE_PIN6) | \ - PIN_ASCR_DISABLED(GPIOE_PIN7) | \ - PIN_ASCR_DISABLED(GPIOE_PIN8) | \ - PIN_ASCR_DISABLED(GPIOE_PIN9) | \ - PIN_ASCR_DISABLED(GPIOE_PIN10) | \ - PIN_ASCR_DISABLED(GPIOE_PIN11) | \ - PIN_ASCR_DISABLED(GPIOE_PIN12) | \ - PIN_ASCR_DISABLED(GPIOE_PIN13) | \ - PIN_ASCR_DISABLED(GPIOE_PIN14) | \ - PIN_ASCR_DISABLED(GPIOE_PIN15)) -#define VAL_GPIOE_LOCKR (PIN_LOCKR_DISABLED(GPIOE_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN15)) - -/* - * GPIOF setup: - * - * PF0 - PIN0 (analog). - * PF1 - PIN1 (analog). - * PF2 - PIN2 (analog). - * PF3 - PIN3 (analog). - * PF4 - PIN4 (analog). - * PF5 - PIN5 (analog). - * PF6 - PIN6 (analog). - * PF7 - PIN7 (analog). - * PF8 - PIN8 (analog). - * PF9 - PIN9 (analog). - * PF10 - PIN10 (analog). - * PF11 - PIN11 (analog). - * PF12 - PIN12 (analog). - * PF13 - PIN13 (analog). - * PF14 - PIN14 (analog). - * PF15 - PIN15 (analog). - */ -#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_PIN0) | \ - PIN_MODE_ANALOG(GPIOF_PIN1) | \ - PIN_MODE_ANALOG(GPIOF_PIN2) | \ - PIN_MODE_ANALOG(GPIOF_PIN3) | \ - PIN_MODE_ANALOG(GPIOF_PIN4) | \ - PIN_MODE_ANALOG(GPIOF_PIN5) | \ - PIN_MODE_ANALOG(GPIOF_PIN6) | \ - PIN_MODE_ANALOG(GPIOF_PIN7) | \ - PIN_MODE_ANALOG(GPIOF_PIN8) | \ - PIN_MODE_ANALOG(GPIOF_PIN9) | \ - PIN_MODE_ANALOG(GPIOF_PIN10) | \ - PIN_MODE_ANALOG(GPIOF_PIN11) | \ - PIN_MODE_ANALOG(GPIOF_PIN12) | \ - PIN_MODE_ANALOG(GPIOF_PIN13) | \ - PIN_MODE_ANALOG(GPIOF_PIN14) | \ - PIN_MODE_ANALOG(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ - PIN_OSPEED_HIGH(GPIOF_PIN1) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ - PIN_ODR_HIGH(GPIOF_PIN1) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) -#define VAL_GPIOF_ASCR (PIN_ASCR_DISABLED(GPIOF_PIN0) | \ - PIN_ASCR_DISABLED(GPIOF_PIN1) | \ - PIN_ASCR_DISABLED(GPIOF_PIN2) | \ - PIN_ASCR_DISABLED(GPIOF_PIN3) | \ - PIN_ASCR_DISABLED(GPIOF_PIN4) | \ - PIN_ASCR_DISABLED(GPIOF_PIN5) | \ - PIN_ASCR_DISABLED(GPIOF_PIN6) | \ - PIN_ASCR_DISABLED(GPIOF_PIN7) | \ - PIN_ASCR_DISABLED(GPIOF_PIN8) | \ - PIN_ASCR_DISABLED(GPIOF_PIN9) | \ - PIN_ASCR_DISABLED(GPIOF_PIN10) | \ - PIN_ASCR_DISABLED(GPIOF_PIN11) | \ - PIN_ASCR_DISABLED(GPIOF_PIN12) | \ - PIN_ASCR_DISABLED(GPIOF_PIN13) | \ - PIN_ASCR_DISABLED(GPIOF_PIN14) | \ - PIN_ASCR_DISABLED(GPIOF_PIN15)) -#define VAL_GPIOF_LOCKR (PIN_LOCKR_DISABLED(GPIOF_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN15)) - -/* - * GPIOG setup: - * - * PG0 - PIN0 (analog). - * PG1 - PIN1 (analog). - * PG2 - PIN2 (analog). - * PG3 - PIN3 (analog). - * PG4 - PIN4 (analog). - * PG5 - PIN5 (analog). - * PG6 - PIN6 (analog). - * PG7 - PIN7 (analog). - * PG8 - PIN8 (analog). - * PG9 - PIN9 (analog). - * PG10 - PIN10 (analog). - * PG11 - PIN11 (analog). - * PG12 - PIN12 (analog). - * PG13 - PIN13 (analog). - * PG14 - PIN14 (analog). - * PG15 - PIN15 (analog). - */ -#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \ - PIN_MODE_ANALOG(GPIOG_PIN1) | \ - PIN_MODE_ANALOG(GPIOG_PIN2) | \ - PIN_MODE_ANALOG(GPIOG_PIN3) | \ - PIN_MODE_ANALOG(GPIOG_PIN4) | \ - PIN_MODE_ANALOG(GPIOG_PIN5) | \ - PIN_MODE_ANALOG(GPIOG_PIN6) | \ - PIN_MODE_ANALOG(GPIOG_PIN7) | \ - PIN_MODE_ANALOG(GPIOG_PIN8) | \ - PIN_MODE_ANALOG(GPIOG_PIN9) | \ - PIN_MODE_ANALOG(GPIOG_PIN10) | \ - PIN_MODE_ANALOG(GPIOG_PIN11) | \ - PIN_MODE_ANALOG(GPIOG_PIN12) | \ - PIN_MODE_ANALOG(GPIOG_PIN13) | \ - PIN_MODE_ANALOG(GPIOG_PIN14) | \ - PIN_MODE_ANALOG(GPIOG_PIN15)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN6) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN7) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN11) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN13) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN15)) -#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN15)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ - PIN_ODR_HIGH(GPIOG_PIN1) | \ - PIN_ODR_HIGH(GPIOG_PIN2) | \ - PIN_ODR_HIGH(GPIOG_PIN3) | \ - PIN_ODR_HIGH(GPIOG_PIN4) | \ - PIN_ODR_HIGH(GPIOG_PIN5) | \ - PIN_ODR_HIGH(GPIOG_PIN6) | \ - PIN_ODR_HIGH(GPIOG_PIN7) | \ - PIN_ODR_HIGH(GPIOG_PIN8) | \ - PIN_ODR_HIGH(GPIOG_PIN9) | \ - PIN_ODR_HIGH(GPIOG_PIN10) | \ - PIN_ODR_HIGH(GPIOG_PIN11) | \ - PIN_ODR_HIGH(GPIOG_PIN12) | \ - PIN_ODR_HIGH(GPIOG_PIN13) | \ - PIN_ODR_HIGH(GPIOG_PIN14) | \ - PIN_ODR_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN7, 0U)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN15, 0U)) -#define VAL_GPIOG_ASCR (PIN_ASCR_DISABLED(GPIOG_PIN0) | \ - PIN_ASCR_DISABLED(GPIOG_PIN1) | \ - PIN_ASCR_DISABLED(GPIOG_PIN2) | \ - PIN_ASCR_DISABLED(GPIOG_PIN3) | \ - PIN_ASCR_DISABLED(GPIOG_PIN4) | \ - PIN_ASCR_DISABLED(GPIOG_PIN5) | \ - PIN_ASCR_DISABLED(GPIOG_PIN6) | \ - PIN_ASCR_DISABLED(GPIOG_PIN7) | \ - PIN_ASCR_DISABLED(GPIOG_PIN8) | \ - PIN_ASCR_DISABLED(GPIOG_PIN9) | \ - PIN_ASCR_DISABLED(GPIOG_PIN10) | \ - PIN_ASCR_DISABLED(GPIOG_PIN11) | \ - PIN_ASCR_DISABLED(GPIOG_PIN12) | \ - PIN_ASCR_DISABLED(GPIOG_PIN13) | \ - PIN_ASCR_DISABLED(GPIOG_PIN14) | \ - PIN_ASCR_DISABLED(GPIOG_PIN15)) -#define VAL_GPIOG_LOCKR (PIN_LOCKR_DISABLED(GPIOG_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN15)) - -/* - * GPIOH setup: - * - * PH0 - PIN0 (analog). - * PH1 - PIN1 (analog). - * PH2 - PIN2 (analog). - * PH3 - PIN3 (analog). - * PH4 - PIN4 (analog). - * PH5 - PIN5 (analog). - * PH6 - PIN6 (analog). - * PH7 - PIN7 (analog). - * PH8 - PIN8 (analog). - * PH9 - PIN9 (analog). - * PH10 - PIN10 (analog). - * PH11 - PIN11 (analog). - * PH12 - PIN12 (analog). - * PH13 - PIN13 (analog). - * PH14 - PIN14 (analog). - * PH15 - PIN15 (analog). - */ -#define VAL_GPIOH_MODER (PIN_MODE_ANALOG(GPIOH_PIN0) | \ - PIN_MODE_ANALOG(GPIOH_PIN1) | \ - PIN_MODE_ANALOG(GPIOH_PIN2) | \ - PIN_MODE_ANALOG(GPIOH_PIN3) | \ - PIN_MODE_ANALOG(GPIOH_PIN4) | \ - PIN_MODE_ANALOG(GPIOH_PIN5) | \ - PIN_MODE_ANALOG(GPIOH_PIN6) | \ - PIN_MODE_ANALOG(GPIOH_PIN7) | \ - PIN_MODE_ANALOG(GPIOH_PIN8) | \ - PIN_MODE_ANALOG(GPIOH_PIN9) | \ - PIN_MODE_ANALOG(GPIOH_PIN10) | \ - PIN_MODE_ANALOG(GPIOH_PIN11) | \ - PIN_MODE_ANALOG(GPIOH_PIN12) | \ - PIN_MODE_ANALOG(GPIOH_PIN13) | \ - PIN_MODE_ANALOG(GPIOH_PIN14) | \ - PIN_MODE_ANALOG(GPIOH_PIN15)) -#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_PIN0) | \ - PIN_OSPEED_HIGH(GPIOH_PIN1) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN15)) -#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN15)) -#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_PIN0) | \ - PIN_ODR_HIGH(GPIOH_PIN1) | \ - PIN_ODR_HIGH(GPIOH_PIN2) | \ - PIN_ODR_HIGH(GPIOH_PIN3) | \ - PIN_ODR_HIGH(GPIOH_PIN4) | \ - PIN_ODR_HIGH(GPIOH_PIN5) | \ - PIN_ODR_HIGH(GPIOH_PIN6) | \ - PIN_ODR_HIGH(GPIOH_PIN7) | \ - PIN_ODR_HIGH(GPIOH_PIN8) | \ - PIN_ODR_HIGH(GPIOH_PIN9) | \ - PIN_ODR_HIGH(GPIOH_PIN10) | \ - PIN_ODR_HIGH(GPIOH_PIN11) | \ - PIN_ODR_HIGH(GPIOH_PIN12) | \ - PIN_ODR_HIGH(GPIOH_PIN13) | \ - PIN_ODR_HIGH(GPIOH_PIN14) | \ - PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN7, 0U)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN15, 0U)) -#define VAL_GPIOH_ASCR (PIN_ASCR_DISABLED(GPIOH_PIN0) | \ - PIN_ASCR_DISABLED(GPIOH_PIN1) | \ - PIN_ASCR_DISABLED(GPIOH_PIN2) | \ - PIN_ASCR_DISABLED(GPIOH_PIN3) | \ - PIN_ASCR_DISABLED(GPIOH_PIN4) | \ - PIN_ASCR_DISABLED(GPIOH_PIN5) | \ - PIN_ASCR_DISABLED(GPIOH_PIN6) | \ - PIN_ASCR_DISABLED(GPIOH_PIN7) | \ - PIN_ASCR_DISABLED(GPIOH_PIN8) | \ - PIN_ASCR_DISABLED(GPIOH_PIN9) | \ - PIN_ASCR_DISABLED(GPIOH_PIN10) | \ - PIN_ASCR_DISABLED(GPIOH_PIN11) | \ - PIN_ASCR_DISABLED(GPIOH_PIN12) | \ - PIN_ASCR_DISABLED(GPIOH_PIN13) | \ - PIN_ASCR_DISABLED(GPIOH_PIN14) | \ - PIN_ASCR_DISABLED(GPIOH_PIN15)) -#define VAL_GPIOH_LOCKR (PIN_LOCKR_DISABLED(GPIOH_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN15)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ +#include_next +#undef STM32L432 +#define STM32L433 \ No newline at end of file diff --git a/platforms/chibios/GENERIC_STM32_L433XC/board/board.mk b/platforms/chibios/GENERIC_STM32_L433XC/board/board.mk index 842e33590594..1250385eb8e2 100644 --- a/platforms/chibios/GENERIC_STM32_L433XC/board/board.mk +++ b/platforms/chibios/GENERIC_STM32_L433XC/board/board.mk @@ -1,8 +1,8 @@ # List of all the board related files. -BOARDSRC = $(BOARD_PATH)/board/board.c +BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC/board.c # Required include directories -BOARDINC = $(BOARD_PATH)/board +BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC # Shared variables ALLCSRC += $(BOARDSRC) From 071b018889a3cb697144491b0f38256869f736ee Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Thu, 11 Mar 2021 15:49:49 +1100 Subject: [PATCH 09/24] l433 specific change --- tmk_core/common/chibios/chibios_config.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tmk_core/common/chibios/chibios_config.h b/tmk_core/common/chibios/chibios_config.h index 1d8ace495565..12904c8b3a45 100644 --- a/tmk_core/common/chibios/chibios_config.h +++ b/tmk_core/common/chibios/chibios_config.h @@ -25,6 +25,10 @@ # define USE_I2CV1 #endif +#if defined(STM32L4xx) +# define PAL_STM32_OSPEED_HIGHEST PAL_STM32_OSPEED_HIGH +#endif + // teensy #if defined(K20x) || defined(KL2x) # define USE_I2CV1 From 181d179b38c5fabe39d4097357ab334e0d3cd8e5 Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Thu, 11 Mar 2021 20:23:05 +1100 Subject: [PATCH 10/24] fix stm32l432xx define --- platforms/chibios/GENERIC_STM32_L433XC/board/board.h | 3 --- platforms/chibios/GENERIC_STM32_L433XC/configs/board.h | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) delete mode 100644 platforms/chibios/GENERIC_STM32_L433XC/board/board.h diff --git a/platforms/chibios/GENERIC_STM32_L433XC/board/board.h b/platforms/chibios/GENERIC_STM32_L433XC/board/board.h deleted file mode 100644 index 1d7feae20271..000000000000 --- a/platforms/chibios/GENERIC_STM32_L433XC/board/board.h +++ /dev/null @@ -1,3 +0,0 @@ -#include_next -#undef STM32L432 -#define STM32L433 \ No newline at end of file diff --git a/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h index f8f0369df85c..ee6f7e610dd0 100644 --- a/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h +++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h @@ -19,4 +19,6 @@ #undef STM32_HSE_BYPASS +#undef STM32L432xx + #define STM32L433xx From de68523915275ead7e0171d3ca6e993dc746177e Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Thu, 11 Mar 2021 20:27:29 +1100 Subject: [PATCH 11/24] remove duplicate #define --- tmk_core/common/chibios/chibios_config.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tmk_core/common/chibios/chibios_config.h b/tmk_core/common/chibios/chibios_config.h index 12904c8b3a45..1d8ace495565 100644 --- a/tmk_core/common/chibios/chibios_config.h +++ b/tmk_core/common/chibios/chibios_config.h @@ -25,10 +25,6 @@ # define USE_I2CV1 #endif -#if defined(STM32L4xx) -# define PAL_STM32_OSPEED_HIGHEST PAL_STM32_OSPEED_HIGH -#endif - // teensy #if defined(K20x) || defined(KL2x) # define USE_I2CV1 From 18441c5de126613e5e3d52f83c1544aa344da0e6 Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Mon, 12 Apr 2021 20:18:46 +1000 Subject: [PATCH 12/24] fix bootloader jump --- platforms/chibios/GENERIC_STM32_L433XC/configs/config.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/platforms/chibios/GENERIC_STM32_L433XC/configs/config.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/config.h index 05e53d65e355..8b85cc517b66 100644 --- a/platforms/chibios/GENERIC_STM32_L433XC/configs/config.h +++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/config.h @@ -23,3 +23,7 @@ #define STM32_BOOTLOADER_ADDRESS 0x1FFF0000 #define PAL_STM32_OSPEED_HIGHEST PAL_STM32_OSPEED_HIGH + +#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP +# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE +#endif \ No newline at end of file From f189e83b2bd507b7d94f0a26b1e0d2802b6c5c02 Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Thu, 15 Apr 2021 16:19:39 +1000 Subject: [PATCH 13/24] move to L443xx and add i2c2, spi2, usart3 to mcuconf.h --- .../chibios/GENERIC_STM32_L433XC/configs/board.h | 8 +++++--- .../GENERIC_STM32_L433XC/configs/mcuconf.h | 15 +++++++++++++++ 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h index ee6f7e610dd0..12b08433acae 100644 --- a/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h +++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h @@ -17,8 +17,10 @@ #include_next "board.h" -#undef STM32_HSE_BYPASS - #undef STM32L432xx -#define STM32L433xx +// Use L443xx define instead of L433xx since ChibiOS defines +// L433xx together with L432x, which does not activate the +// GPIO H ports and does not enable I2C2 and SPI2 +// Until the bug is fixed in ChibiOS, this should not change +#define STM32L443xx diff --git a/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h index 68ad3b647c93..07d2453f0f2c 100644 --- a/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h +++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h @@ -156,10 +156,13 @@ * I2C driver system settings. */ #define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE #define STM32_I2C_USE_I2C3 FALSE #define STM32_I2C_BUSY_TIMEOUT 50 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C1_IRQ_PRIORITY 5 @@ -207,9 +210,12 @@ * SPI driver system settings. */ #define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE #define STM32_SPI_USE_SPI3 FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_SPI_SPI1_DMA_PRIORITY 1 @@ -234,10 +240,13 @@ */ #define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") /* @@ -259,4 +268,10 @@ #define STM32_WSPI_USE_QUADSPI1 FALSE #define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +/* + * SDMMC drive system settings. + */ +#define STM32_HAS_SDMMC1 FALSE +#define STM32_SDC_SDMMC1_DMA_MSK STM32_DMA_STREAM_ID(2, 4) + #endif /* MCUCONF_H */ From 73ee84b08c16b35c24341038acbcfb7a1b6b1f14 Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Thu, 15 Apr 2021 16:33:36 +1000 Subject: [PATCH 14/24] move to L443 --- platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h index 07d2453f0f2c..4657f3a7db6e 100644 --- a/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h +++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h @@ -29,7 +29,7 @@ #define MCUCONF_H #define STM32L4xx_MCUCONF -#define STM32L433_MCUCONF +#define STM32L443_MCUCONF /* * HAL driver system settings. From d732b85e0b0145060f463687a31f681418f0252e Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Thu, 15 Apr 2021 16:36:48 +1000 Subject: [PATCH 15/24] move to L443 --- .../chibios/GENERIC_STM32_L433XC/configs/mcuconf.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h index 4657f3a7db6e..f76618cde91d 100644 --- a/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h +++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h @@ -72,8 +72,10 @@ */ #define STM32_USART1SEL STM32_USART1SEL_SYSCLK #define STM32_USART2SEL STM32_USART2SEL_SYSCLK +#define STM32_USART3SEL STM32_USART3SEL_SYSCLK #define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK #define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK +#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK #define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 @@ -109,6 +111,7 @@ #define STM32_IRQ_USART1_PRIORITY 12 #define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART3_PRIORITY 12 #define STM32_IRQ_LPUART1_PRIORITY 12 /* @@ -161,13 +164,15 @@ #define STM32_I2C_BUSY_TIMEOUT 50 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 #define STM32_I2C_I2C3_IRQ_PRIORITY 5 #define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 #define STM32_I2C_I2C3_DMA_PRIORITY 3 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") @@ -201,9 +206,11 @@ */ #define STM32_SERIAL_USE_USART1 FALSE #define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_LPUART1 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_LPUART1_PRIORITY 12 /* @@ -219,8 +226,10 @@ #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 #define STM32_SPI_SPI3_IRQ_PRIORITY 10 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") From a9eec9aa3baee697921132846bb22be04c0cb21d Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Fri, 16 Apr 2021 12:59:28 +1000 Subject: [PATCH 16/24] fix sdmmc in mcuconf.h --- .../GENERIC_STM32_L433XC/configs/mcuconf.h | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h index f76618cde91d..948c740f6e2b 100644 --- a/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h +++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/mcuconf.h @@ -201,6 +201,18 @@ #define STM32_RTC_CR_INIT 0 #define STM32_RTC_TAMPCR_INIT 0 +/* + * SDMMC drive system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) + /* * SERIAL driver system settings. */ @@ -277,10 +289,4 @@ #define STM32_WSPI_USE_QUADSPI1 FALSE #define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -/* - * SDMMC drive system settings. - */ -#define STM32_HAS_SDMMC1 FALSE -#define STM32_SDC_SDMMC1_DMA_MSK STM32_DMA_STREAM_ID(2, 4) - #endif /* MCUCONF_H */ From 51369542d91a1a440bece2feb6d3644968945a96 Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Fri, 16 Apr 2021 16:01:14 +1000 Subject: [PATCH 17/24] include STM32L443 --- quantum/mcu_selection.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/quantum/mcu_selection.mk b/quantum/mcu_selection.mk index e73f7a780240..42abd674a139 100644 --- a/quantum/mcu_selection.mk +++ b/quantum/mcu_selection.mk @@ -435,7 +435,7 @@ ifneq ($(findstring STM32G474, $(MCU)),) UF2_FAMILY ?= STM32G4 endif -ifneq ($(findstring STM32L433, $(MCU)),) +ifneq (,$(filter $(MCU),STM32L433 STM32L443)) # Cortex version MCU = cortex-m4 From deb8ed0f69745f555177aff2a3bddeb37eebd1b7 Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Sun, 18 Apr 2021 15:24:51 +1000 Subject: [PATCH 18/24] add L443 --- data/schemas/keyboard.jsonschema | 6 +++++- lib/python/qmk/constants.py | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/data/schemas/keyboard.jsonschema b/data/schemas/keyboard.jsonschema index 77ef174773e0..9cf18837fe56 100644 --- a/data/schemas/keyboard.jsonschema +++ b/data/schemas/keyboard.jsonschema @@ -25,7 +25,11 @@ }, "processor": { "type": "string", - "enum": ["cortex-m0", "cortex-m0plus", "cortex-m3", "cortex-m4", "MKL26Z64", "MK20DX128", "MK20DX256", "MK66F18", "STM32F042", "STM32F072", "STM32F103", "STM32F303", "STM32F401", "STM32F411", "STM32F446", "STM32G431", "STM32G474", "STM32L433", "atmega16u2", "atmega32u2", "atmega16u4", "atmega32u4", "at90usb162", "at90usb646", "at90usb647", "at90usb1286", "at90usb1287", "atmega32a", "atmega328p", "atmega328", "attiny85", "unknown"] +<<<<<<< HEAD + "enum": ["cortex-m0", "cortex-m0plus", "cortex-m3", "cortex-m4", "MKL26Z64", "MK20DX128", "MK20DX256", "MK66F18", "STM32F042", "STM32F072", "STM32F103", "STM32F303", "STM32F401", "STM32F411", "STM32F446", "STM32G431", "STM32G474", "STM32L433", "STM32L443", "atmega16u2", "atmega32u2", "atmega16u4", "atmega32u4", "at90usb162", "at90usb646", "at90usb647", "at90usb1286", "at90usb1287", "atmega32a", "atmega328p", "atmega328", "attiny85", "unknown"] +======= + "enum": ["cortex-m0", "cortex-m0plus", "cortex-m3", "cortex-m4", "MKL26Z64", "MK20DX128", "MK20DX256", "MK66F18", "STM32F042", "STM32F072", "STM32F103", "STM32F303", "STM32F401", "STM32F411", "STM32G431", "STM32G474", "STM32L433", "STM32L443", "atmega16u2", "atmega32u2", "atmega16u4", "atmega32u4", "at90usb162", "at90usb646", "at90usb647", "at90usb1286", "at90usb1287", "atmega32a", "atmega328p", "atmega328", "attiny85", "unknown"] +>>>>>>> add L443 }, "board": { "type": "string", diff --git a/lib/python/qmk/constants.py b/lib/python/qmk/constants.py index 394801cb53ff..49e5e0eb42d0 100644 --- a/lib/python/qmk/constants.py +++ b/lib/python/qmk/constants.py @@ -10,7 +10,7 @@ MAX_KEYBOARD_SUBFOLDERS = 5 # Supported processor types -CHIBIOS_PROCESSORS = 'cortex-m0', 'cortex-m0plus', 'cortex-m3', 'cortex-m4', 'MKL26Z64', 'MK20DX128', 'MK20DX256', 'MK66F18', 'STM32F042', 'STM32F072', 'STM32F103', 'STM32F303', 'STM32F401', 'STM32F411', 'STM32F446', 'STM32G431', 'STM32G474', 'STM32L433' +CHIBIOS_PROCESSORS = 'cortex-m0', 'cortex-m0plus', 'cortex-m3', 'cortex-m4', 'MKL26Z64', 'MK20DX128', 'MK20DX256', 'MK66F18', 'STM32F042', 'STM32F072', 'STM32F103', 'STM32F303', 'STM32F401', 'STM32F411', 'STM32F446', 'STM32G431', 'STM32G474', 'STM32L433', 'STM32L443' LUFA_PROCESSORS = 'at90usb162', 'atmega16u2', 'atmega32u2', 'atmega16u4', 'atmega32u4', 'at90usb646', 'at90usb647', 'at90usb1286', 'at90usb1287', None VUSB_PROCESSORS = 'atmega32a', 'atmega328p', 'atmega328', 'attiny85' From 7d39d978db9c8f5e22889f498f25941f84566909 Mon Sep 17 00:00:00 2001 From: Xelus22 <17491233+Xelus22@users.noreply.github.com> Date: Mon, 19 Apr 2021 05:30:41 +0000 Subject: [PATCH 19/24] Include L443 in compatible microcontrollers Co-authored-by: Nick Brassel --- docs/ja/compatible_microcontrollers.md | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/ja/compatible_microcontrollers.md b/docs/ja/compatible_microcontrollers.md index d86941c72ab6..b675b038d271 100644 --- a/docs/ja/compatible_microcontrollers.md +++ b/docs/ja/compatible_microcontrollers.md @@ -37,6 +37,7 @@ QMK は十分な容量のフラッシュメモリを備えた USB 対応 AVR ま * [STM32G431](https://www.st.com/en/microcontrollers-microprocessors/stm32g4x1.html) * [STM32G474](https://www.st.com/en/microcontrollers-microprocessors/stm32g4x4.html) * [STM32L433](https://www.st.com/en/microcontrollers-microprocessors/stm32l4x3.html) +* [STM32L443](https://www.st.com/en/microcontrollers-microprocessors/stm32l4x3.html) ### NXP (Kinetis) From 06ed5de6124459d6f7406d5c0f3a93ffdc40bc28 Mon Sep 17 00:00:00 2001 From: Xelus22 <17491233+Xelus22@users.noreply.github.com> Date: Mon, 19 Apr 2021 05:31:12 +0000 Subject: [PATCH 20/24] Include L443 in compatible microcontrollers Co-authored-by: Nick Brassel --- docs/compatible_microcontrollers.md | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/compatible_microcontrollers.md b/docs/compatible_microcontrollers.md index f04748a85289..0f5b140de0b5 100644 --- a/docs/compatible_microcontrollers.md +++ b/docs/compatible_microcontrollers.md @@ -32,6 +32,7 @@ You can also use any ARM chip with USB that [ChibiOS](https://www.chibios.org) s * [STM32G431](https://www.st.com/en/microcontrollers-microprocessors/stm32g4x1.html) * [STM32G474](https://www.st.com/en/microcontrollers-microprocessors/stm32g4x4.html) * [STM32L433](https://www.st.com/en/microcontrollers-microprocessors/stm32l4x3.html) + * [STM32L443](https://www.st.com/en/microcontrollers-microprocessors/stm32l4x3.html) ### NXP (Kinetis) From c31025e82d3554c5a2bf6eb88c3307a231e62b58 Mon Sep 17 00:00:00 2001 From: Xelus22 <17491233+Xelus22@users.noreply.github.com> Date: Mon, 19 Apr 2021 05:31:40 +0000 Subject: [PATCH 21/24] Update config bootloader jump description Co-authored-by: Nick Brassel --- platforms/chibios/GENERIC_STM32_L433XC/configs/config.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/platforms/chibios/GENERIC_STM32_L433XC/configs/config.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/config.h index 8b85cc517b66..c27c61b19aa4 100644 --- a/platforms/chibios/GENERIC_STM32_L433XC/configs/config.h +++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/config.h @@ -15,10 +15,7 @@ */ /* Address for jumping to bootloader on STM32 chips. */ -/* It is chip dependent, the correct number can be looked up here (page 175): - * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf - * This also requires a patch to chibios: - * /tmk_core/tool/chibios/ch-bootloader-jump.patch +/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606. */ #define STM32_BOOTLOADER_ADDRESS 0x1FFF0000 @@ -26,4 +23,4 @@ #ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP # define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE -#endif \ No newline at end of file +#endif From 222fbe99c38cab4d996688d6c5467c0da9d935dd Mon Sep 17 00:00:00 2001 From: Xelus22 <17491233+Xelus22@users.noreply.github.com> Date: Mon, 19 Apr 2021 05:32:05 +0000 Subject: [PATCH 22/24] Update ChibiOS define reasoning Co-authored-by: Nick Brassel --- platforms/chibios/GENERIC_STM32_L433XC/configs/board.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h b/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h index 12b08433acae..51f9724f942a 100644 --- a/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h +++ b/platforms/chibios/GENERIC_STM32_L433XC/configs/board.h @@ -19,8 +19,6 @@ #undef STM32L432xx -// Use L443xx define instead of L433xx since ChibiOS defines -// L433xx together with L432x, which does not activate the -// GPIO H ports and does not enable I2C2 and SPI2 -// Until the bug is fixed in ChibiOS, this should not change +// Pretend that we're an L443xx as the ChibiOS definitions for L432/L433 mistakenly don't enable GPIOH, I2C2, or SPI2. +// Until ChibiOS upstream is fixed, this should be kept at L443, as nothing in QMK currently utilises the crypto peripheral on the L443. #define STM32L443xx From a2b49be0a68e18534b771f5ba9789788e3a14077 Mon Sep 17 00:00:00 2001 From: Xelus22 <17491233+Xelus22@users.noreply.github.com> Date: Mon, 26 Apr 2021 02:44:00 +0000 Subject: [PATCH 23/24] Update quantum/mcu_selection.mk Co-authored-by: Nick Brassel --- quantum/mcu_selection.mk | 3 +++ 1 file changed, 3 insertions(+) diff --git a/quantum/mcu_selection.mk b/quantum/mcu_selection.mk index 42abd674a139..9268c4522e61 100644 --- a/quantum/mcu_selection.mk +++ b/quantum/mcu_selection.mk @@ -468,6 +468,9 @@ ifneq (,$(filter $(MCU),STM32L433 STM32L443)) # Options to pass to dfu-util when flashing DFU_ARGS ?= -d 0483:DF11 -a 0 -s 0x08000000:leave DFU_SUFFIX_ARGS ?= -v 0483 -p DF11 + + # UF2 settings + UF2_FAMILY ?= STM32L4 endif ifneq (,$(filter $(MCU),at90usb162 atmega16u2 atmega32u2 atmega16u4 atmega32u4 at90usb646 at90usb647 at90usb1286 at90usb1287)) From d0bcbb63c25e5da20d03baa149662781d2c6fa30 Mon Sep 17 00:00:00 2001 From: Xelus22 Date: Mon, 26 Apr 2021 12:57:33 +1000 Subject: [PATCH 24/24] fix git conflict --- data/schemas/keyboard.jsonschema | 4 ---- 1 file changed, 4 deletions(-) diff --git a/data/schemas/keyboard.jsonschema b/data/schemas/keyboard.jsonschema index 9cf18837fe56..c335f49d52fd 100644 --- a/data/schemas/keyboard.jsonschema +++ b/data/schemas/keyboard.jsonschema @@ -25,11 +25,7 @@ }, "processor": { "type": "string", -<<<<<<< HEAD "enum": ["cortex-m0", "cortex-m0plus", "cortex-m3", "cortex-m4", "MKL26Z64", "MK20DX128", "MK20DX256", "MK66F18", "STM32F042", "STM32F072", "STM32F103", "STM32F303", "STM32F401", "STM32F411", "STM32F446", "STM32G431", "STM32G474", "STM32L433", "STM32L443", "atmega16u2", "atmega32u2", "atmega16u4", "atmega32u4", "at90usb162", "at90usb646", "at90usb647", "at90usb1286", "at90usb1287", "atmega32a", "atmega328p", "atmega328", "attiny85", "unknown"] -======= - "enum": ["cortex-m0", "cortex-m0plus", "cortex-m3", "cortex-m4", "MKL26Z64", "MK20DX128", "MK20DX256", "MK66F18", "STM32F042", "STM32F072", "STM32F103", "STM32F303", "STM32F401", "STM32F411", "STM32G431", "STM32G474", "STM32L433", "STM32L443", "atmega16u2", "atmega32u2", "atmega16u4", "atmega32u4", "at90usb162", "at90usb646", "at90usb647", "at90usb1286", "at90usb1287", "atmega32a", "atmega328p", "atmega328", "attiny85", "unknown"] ->>>>>>> add L443 }, "board": { "type": "string",