probe-rs · bugadani · Jun 5, 2024 · Jun 5, 2024 · Jun 5, 2024 · Jun 5, 2024
diff --git a/probe-rs-target/src/chip.rs b/probe-rs-target/src/chip.rs
@@ -42,11 +42,14 @@ pub struct Jtag {
 /// This describes an exact chip variant, including the cores, flash and memory size. For example,
 /// the `nRF52832` chip has two variants, `nRF52832_xxAA` and `nRF52832_xxBB`. For this case,
 /// the struct will correspond to one of the variants, e.g. `nRF52832_xxAA`.
-#[derive(Debug, Clone, Serialize, Deserialize)]
+#[derive(Debug, Clone, Serialize, Deserialize, PartialEq)]
 pub struct Chip {
     /// This is the name of the chip in base form.
     /// E.g. `nRF52832`.
     pub name: String,
+    /// A list of target names that are identical to this target.
+    #[serde(default)]
+    pub aliases: Vec<String>,
     /// The `PART` register of the chip.
     /// This value can be determined via the `cli info` command.
     pub part: Option<u16>,
@@ -98,6 +101,7 @@ impl Chip {
     pub fn generic_arm(name: &str, core_type: CoreType) -> Self {
         Chip {
             name: name.to_string(),
+            aliases: vec![],
             part: None,
             svd: None,
             documentation: HashMap::new(),
@@ -116,7 +120,7 @@ impl Chip {
 }
 
 /// An individual core inside a chip
-#[derive(Debug, Clone, Serialize, Deserialize)]
+#[derive(Debug, Clone, Serialize, Deserialize, PartialEq)]
 pub struct Core {
     /// The core name.
     pub name: String,
@@ -131,7 +135,7 @@ pub struct Core {
 }
 
 /// The data required to access a core
-#[derive(Debug, Clone, Serialize, Deserialize)]
+#[derive(Debug, Clone, Serialize, Deserialize, PartialEq)]
 pub enum CoreAccessOptions {
     /// ARM specific options
     Arm(ArmCoreAccessOptions),
@@ -142,7 +146,7 @@ pub enum CoreAccessOptions {
 }
 
 /// The data required to access an ARM core
-#[derive(Debug, Clone, Serialize, Deserialize, Default)]
+#[derive(Debug, Clone, Serialize, Deserialize, Default, PartialEq)]
 pub struct ArmCoreAccessOptions {
     /// The access port number to access the core
     pub ap: u8,
@@ -160,7 +164,7 @@ pub struct ArmCoreAccessOptions {
 }
 
 /// The data required to access a Risc-V core
-#[derive(Debug, Clone, Serialize, Deserialize)]
+#[derive(Debug, Clone, Serialize, Deserialize, PartialEq)]
 pub struct RiscvCoreAccessOptions {
     /// The hart id
     pub hart_id: Option<u32>,
@@ -170,7 +174,7 @@ pub struct RiscvCoreAccessOptions {
 }
 
 /// The data required to access an Xtensa core
-#[derive(Debug, Clone, Serialize, Deserialize)]
+#[derive(Debug, Clone, Serialize, Deserialize, PartialEq)]
 pub struct XtensaCoreAccessOptions {
     /// The JTAG TAP index of the core's debug module
     pub jtag_tap: Option<usize>,

diff --git a/probe-rs/src/config/registry.rs b/probe-rs/src/config/registry.rs
@@ -92,6 +92,7 @@ fn add_generic_targets(vec: &mut Vec<ChipFamily>) {
             generated_from_pack: false,
             variants: vec![Chip {
                 name: "riscv".to_owned(),
+                aliases: vec![],
                 part: None,
                 svd: None,
                 documentation: HashMap::new(),
@@ -154,20 +155,47 @@ impl Registry {
         let mut partial_matches = Vec::new();
         for family in self.families.iter() {
             for variant in family.variants.iter() {
-                if match_name_prefix(&variant.name, name) {
-                    if variant.name.len() == name.len() {
-                        tracing::debug!("Exact match for chip name: {}", variant.name);
-                        exact_matches += 1;
-                    } else {
-                        tracing::debug!("Partial match for chip name: {}", variant.name);
+                if !match_name_prefix(&variant.name, name) {
+                    continue;
+                }
+
+                // Has the user explicitly requested the group name?
+                // Is there a matching alias in this variant?
+                if !variant.name.eq_ignore_ascii_case(name)
+                    && !variant.aliases.is_empty()
+                    && !variant
+                        .aliases
+                        .iter()
+                        .any(|alias| ignore_case_starts_with(alias, name))
+                {
+                    tracing::debug!("No alias match for chip name: {}", variant.name);
+                    continue;
+                }
+
+                if variant.name.len() == name.len() {
+                    tracing::debug!("Exact match for chip name: {}", variant.name);
+                    exact_matches += 1;
+                } else {
+                    tracing::debug!("Partial match for chip name: {}", variant.name);
+
+                    if variant.aliases.is_empty() {
                         partial_matches.push(variant.name.as_str());
-                        // Only select partial match if we don't have an exact match yet
-                        if exact_matches > 0 {
-                            continue;
-                        }
+                    } else {
+                        partial_matches.extend(
+                            variant
+                                .aliases
+                                .iter()
+                                .filter(|alias| ignore_case_starts_with(alias, name))
+                                .map(|alias| alias.as_str()),
+                        );
+                    }
+
+                    // Only select partial match if we don't have an exact match yet
+                    if exact_matches > 0 {
+                        continue;
                     }
-                    selected_family_and_chip = Some((family, variant));
                 }
+                selected_family_and_chip = Some((family, variant));
             }
         }
 
@@ -252,7 +280,11 @@ impl Registry {
         for family in &self.families {
             for variant in family.variants.iter() {
                 if match_name_prefix(name, &variant.name) {
-                    targets.push(variant.name.to_string());
+                    if variant.aliases.is_empty() {
+                        targets.push(variant.name.to_string());
+                    } else {
+                        targets.extend(variant.aliases.iter().map(|a| a.to_string()));
+                    }
                 }
             }
         }
@@ -419,6 +451,20 @@ fn match_name_prefix(pattern: &str, name: &str) -> bool {
     true
 }
 
+fn ignore_case_starts_with(name: &str, prefix: &str) -> bool {
+    if name.len() < prefix.len() {
+        return false;
+    }
+
+    for (n, p) in name.chars().zip(prefix.chars()) {
+        if !n.eq_ignore_ascii_case(&p) {
+            return false;
+        }
+    }
+
+    true
+}
+
 #[cfg(test)]
 mod tests {
     use super::*;

diff --git a/probe-rs/targets/AIR32F1_Series.yaml b/probe-rs/targets/AIR32F1_Series.yaml
@@ -27,7 +27,10 @@ variants:
     - main
   flash_algorithms:
   - air32f103cbt6
-- name: AIR32F103CC
+- name: AIR32F103xx
+  aliases:
+  - AIR32F103CC
+  - AIR32F103RP
   cores:
   - name: main
     type: armv7m
@@ -77,31 +80,6 @@ variants:
     - main
   flash_algorithms:
   - air32f10x_1024
-- name: AIR32F103RP
-  cores:
-  - name: main
-    type: armv7m
-    core_access_options: !Arm
-      ap: 0
-      psel: 0x0
-  memory_map:
-  - !Ram
-    name: IRAM1
-    range:
-      start: 0x20000000
-      end: 0x20018000
-    cores:
-    - main
-  - !Nvm
-    name: IROM1
-    range:
-      start: 0x8000000
-      end: 0x8040000
-    is_boot_memory: true
-    cores:
-    - main
-  flash_algorithms:
-  - air32f103cct6
 - name: AIR32F103VE
   cores:
   - name: main
@@ -126,7 +104,7 @@ variants:
     cores:
     - main
   flash_algorithms:
-  - air32f103vet6
+  - air32f103cct6
 flash_algorithms:
 - name: air32f103cbt6
   description: Air32F103CBT6
@@ -197,26 +175,3 @@ flash_algorithms:
     - size: 0x1000
       address: 0x0
   transfer_encoding: raw
-- name: air32f103vet6
-  description: Air32F103VET6
-  default: true
-  instructions: ELUDRtgMwARHTExEIGAAIEZMIGBGSGBgRkhgYCBGwGkA8AQAQLlF8lVQQ0wgYAYgYGBA9v9woGAAIBC9AUY7SABpQPCAADlKEGEAIHBHN0gAaUDwBAA1SQhhCEYAaUDwQAAIYQPgSvaqIDNJCGAvSMBoAPABAAAo9dEsSABpIPAEACpJCGEAIHBHAUYnSABpQPACACVKEGEQRkFhAGlA8EAAEGED4Er2qiAjShBgH0jAaADwAQAAKPXRHEgAaSDwAgAaShBhACBwRxC1A0ZIHCDwAQEj4BVIAGlA8AEAE0wgYRCIGIAAvxBIwGgA8AEAACj50Q1IAGkg8AEAC0wgYSBGwGgA8BQAMLEgRsBoQPAUAOBgASAQvZsckhyJHgAp2dEAIPfnAAAEAAAAACACQCMBZ0Wrie/NADAAQAAAAAAAAAAA
-  load_address: 0x20000020
-  pc_init: 0x1
-  pc_uninit: 0x3d
-  pc_program_page: 0xcb
-  pc_erase_sector: 0x8b
-  pc_erase_all: 0x4f
-  data_section_offset: 0x13c
-  flash_properties:
-    address_range:
-      start: 0x8000000
-      end: 0x8080000
-    page_size: 0x400
-    erased_byte_value: 0xff
-    program_page_timeout: 100
-    erase_sector_timeout: 500
-    sectors:
-    - size: 0x800
-      address: 0x0
-  transfer_encoding: raw