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Debugger: Slightly relax the RISC-V restriction when handling of restart request. #1569

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merged 3 commits into from
Mar 19, 2023
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Debugger: Slightly relax the RISC-V restriction when handling of restart request. #1569

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6ce5416
Slightly relax the RISC-V restriction when handling `restart` reques…
noppej Mar 15, 2023
98cc355
CHANGELOG
noppej Mar 15, 2023
15f1943
Merge branch 'master' into riscv_restart
noppej Mar 16, 2023
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Slightly relax the RISC-V restriction when handling restart reques… 
…t. Allows restart, but does not re-flash.
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@noppej
noppej committed Mar 15, 2023
commit 6ce5416b7185b1dc9dd497ba9ca0c2739f81305f
3 changes: 3 additions & 0 deletions CHANGELOG.md
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Expand Up @@ -43,6 +43,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0

- probe-rs-debugger: Remove `restart-after-flashing` option, and make it the default behaviour. (#1550)

- probe-rs-debugger: Slightly relax the RISC-V restriction when handling `restart` request. Allows restart, but does not re-flash. (#)

### Added

- Added EFM32TG11B family targets #1420
Expand All @@ -55,6 +57,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Add default sequence 'debug_core_stop', which disables debugging when disconneting from ARM cores by default. (#1525)

- probe-rs-debugger: Initial support for 'gdb-like' commands to be typed into VSCode Debug Console REPL. (#1552)

- The `help` command will list available commands, and arguments.
- Command completions are supported for the individual commands, but not for the arguments.
- Additional commands can be added in the future, as required, but will benefit from some refactoring to share code with functionality that is already implementated in `dap_adapter.rs` for MS DAP requests.
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30 changes: 16 additions & 14 deletions debugger/src/server/debugger.rs
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Expand Up @@ -228,24 +228,26 @@ impl Debugger {
}
"threads" => debug_adapter.threads(&mut target_core, &request),
"restart" => {
if target_core.core.architecture() == Architecture::Riscv {
if target_core.core.architecture() == Architecture::Riscv
&& self.config.flashing_config.flashing_enabled
{
debug_adapter.show_message(
MessageSeverity::Information,
"In-session `restart` is not currently supported for RISC-V.",
"Re-flashing the target during on-session `restart` is not currently supported for RISC-V. Flashing will be disabled for the remainder of this session.",
);
Ok(())
} else {
// Reset RTT so that the link can be re-established
target_core.core_data.rtt_connection = None;
let result = target_core
.core
.halt(Duration::from_millis(500))
.map_err(|error| anyhow!("Failed to halt core: {}", error))
.and(Ok(()));

debug_session = DebugSessionStatus::Restart(request);
result
self.config.flashing_config.flashing_enabled = false;
}

// Reset RTT so that the link can be re-established
target_core.core_data.rtt_connection = None;
let result = target_core
.core
.halt(Duration::from_millis(500))
.map_err(|error| anyhow!("Failed to halt core: {}", error))
.and(Ok(()));

debug_session = DebugSessionStatus::Restart(request);
result
}
"setBreakpoints" => debug_adapter.set_breakpoints(&mut target_core, &request),
"setInstructionBreakpoints" => {
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