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fpga.idol
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// FPGA server IPC interface
Interface(
name: "Fpga",
ops: {
"device_enabled": (
doc: "Return true if the FPGA is enabled, false otherwise",
args: {
"device_index": "u8",
},
reply: Result(
ok: "bool",
err: CLike("FpgaError"),
),
),
"set_device_enabled": (
doc: "Enable or disable the FPGA",
args: {
"device_index": "u8",
"enabled": "bool",
},
reply: Result(
ok: "()",
err: CLike("FpgaError"),
),
),
"reset_device": (
doc: "Reset the FPGA",
args: {
"device_index": "u8",
},
reply: Result(
ok: "()",
err: CLike("FpgaError"),
),
),
"device_state": (
doc: "Return the current device state",
args: {
"device_index": "u8",
},
reply: Result(
ok: (
type: "DeviceState",
recv: FromPrimitive("u8"),
),
err: CLike("FpgaError"),
),
),
"device_id": (
doc: "Return the device id, if applicable",
args: {
"device_index": "u8",
},
reply: Result(
ok: "u32",
err: CLike("FpgaError"),
),
),
"start_bitstream_load": (
doc: "Prepare the device to load a bitstream",
args: {
"device_index": "u8",
"bitstream_type": (
type: "BitstreamType",
recv: FromPrimitive("u8"),
)
},
reply: Result(
ok: "()",
err: CLike("FpgaError"),
),
),
"continue_bitstream_load": (
doc: "Load the next chunk of the bitstream",
args: {},
leases: {
"data": (type: "[u8]", read: true, max_len: Some(128)),
},
reply: Result(
ok: "()",
err: CLike("FpgaError"),
),
),
"finish_bitstream_load": (
doc: "Finish loading a bitstream",
args: {},
reply: Result(
ok: "()",
err: CLike("FpgaError"),
),
),
"user_design_enabled": (
doc: "Return true if the user design reset is released, false otherwise",
args: {
"device_index": "u8",
},
reply: Result(
ok: "bool",
err: CLike("FpgaError"),
),
),
"set_user_design_enabled": (
doc: "Set the reset state for the user_design",
args: {
"device_index": "u8",
"enabled": "bool",
},
reply: Result(
ok: "()",
err: CLike("FpgaError"),
),
),
"reset_user_design": (
doc: "Reset the user_design",
args: {
"device_index": "u8",
},
reply: Result(
ok: "()",
err: CLike("FpgaError"),
),
),
"user_design_read": (
doc: "Read N bytes from the user design, starting at the given address",
args: {
"device_index": "u8",
"op": (
type: "ReadOp",
recv: FromPrimitive("u8"),
),
"addr": "u16",
},
leases: {
"data": (type: "[u8]", write: true),
},
reply: Result(
ok: "()",
err: CLike("FpgaError"),
)
),
"user_design_write": (
doc: "Write N bytes to the user design, starting at the given address",
args: {
"device_index": "u8",
"op": (
type: "WriteOp",
recv: FromPrimitive("u8"),
),
"addr": "u16",
},
leases: {
"data": (type: "[u8]", read: true),
},
reply: Result(
ok: "()",
err: CLike("FpgaError"),
)
),
"user_design_read_reg": (
doc: "Read 1 byte from the user design, at the given address",
args: {
"device_index": "u8",
"addr": "u16",
},
reply: Result(
ok: "u8",
err: CLike("FpgaError"),
)
),
"user_design_write_reg": (
doc: "Write 1 byte to the user design, at the given address",
args: {
"device_index": "u8",
"op": (
type: "WriteOp",
recv: FromPrimitive("u8"),
),
"addr": "u16",
"value": "u8",
},
reply: Result(
ok: "()",
err: CLike("FpgaError"),
)
),
"lock": (
doc: "Take exclusive control of this FPGA or the user design.",
args: {
"device_index": "u8",
},
reply: Result(
ok: "()",
err: CLike("FpgaError"),
),
),
"release": (
doc: "Release a previously acquired lock.",
args: {},
reply: Result(
ok: "()",
err: CLike("FpgaError"),
),
),
},
)