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    40 repositories

    • Validation

      Public
      Raptor Compiler Validation tests
      sw
      Verilog
      •
      Other
      •15•2•0•0•Updated Oct 6, 2024Oct 6, 2024

    • FPGA_PRIMITIVES_MODELS

      Public
      sw
      Verilog
      •
      Other
      •5•2•0•1•Updated Oct 6, 2024Oct 6, 2024

    • Raptor

      Public
      Raptor end-to-end FPGA Compiler and GUI
      sw
      Verilog
      •
      Other
      •22•61•1•0•Updated Oct 5, 2024Oct 5, 2024

    • yosys_verific_rs

      Public
      Yosys + (Optional) Verific Integration
      sw
      Verilog
      •
      Other
      •6•4•0•1•Updated Oct 5, 2024Oct 5, 2024

    • Backend

      Public
      Compiler backend from packing to bitstream generation.
      routingpackingswplacementtiming-analysisbitstream-generationfpga-complete-flow
      C++
      •
      Other
      •3•3•0•1•Updated Oct 4, 2024Oct 4, 2024

    • rapid_power_estimator

      Public
      Rapid Power Estimator For Raptor
      Python
      •
      Other
      •2•1•0•0•Updated Oct 4, 2024Oct 4, 2024

    • Jira_Testcase

      Public
      sw
      Verilog
      •
      Other
      •16•0•0•0•Updated Oct 4, 2024Oct 4, 2024

    • zephyr_rs

      Public
      Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.
      C
      •
      Apache License 2.0
      •6.5k•0•0•1•Updated Oct 4, 2024Oct 4, 2024

    • FOEDAG_rs

      Public
      Raptor's GUI
      sw
      C++
      •
      Other
      •4•5•0•0•Updated Oct 3, 2024Oct 3, 2024

    • FOEDAG

      Public
      Framework Open EDA Gui
      ossw
      C++
      •
      Other
      •29•58•14•0•Updated Oct 3, 2024Oct 3, 2024

    • Raptor_Tools

      Public
      sw
      Verilog
      •
      Other
      •3•1•0•0•Updated Oct 3, 2024Oct 3, 2024

    • device_modeling

      Public
      Verilog
      •
      Other
      •8•2•0•0•Updated Oct 3, 2024Oct 3, 2024

    • ArchBench

      Public
      Architecture file validation testcase - RTL to Bitstream simulation flow
      sw
      Verilog
      •
      Other
      •2•1•0•0•Updated Oct 2, 2024Oct 2, 2024

    • RaptorBuilds

      Public
      0•0•0•0•Updated Oct 2, 2024Oct 2, 2024

    • IP_Catalog

      Public
      IP Catalog for Raptor.
      sw
      Verilog
      •
      Other
      •8•4•0•0•Updated Sep 30, 2024Sep 30, 2024

    • yosys_rs

      Public
      Raptor's Yosys hard fork. Contains optimizations
      sw
      C++
      •
      Other
      •4•1•1•0•Updated Sep 29, 2024Sep 29, 2024

    • yosys-rs-plugin

      Public
      Rapidsilicon's Yosys Plugin
      sw
      Verilog
      •
      Other
      •4•0•0•0•Updated Sep 26, 2024Sep 26, 2024

    • 1st-CLaaS

      Public
      Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications
      os
      C
      •
      BSD 3-Clause "New" or "Revised" License
      •42•196•15•21•Updated Aug 1, 2024Aug 1, 2024

    • Virtual-FPGA-Lab

      Public
      This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, under FOSSi Foundation.
      open-sourceosgsoctl-verilogmakerchipvirtual-fpga
      Tcl
      •
      MIT License
      •23•133•1•3•Updated Jul 12, 2024Jul 12, 2024

    • RTL_Benchmark

      Public
      This repository contains the benchmarks.
      sw
      Verilog
      •
      Other
      •3•4•4•0•Updated May 30, 2024May 30, 2024

    • raptor_downloader

      Public
      0•0•0•0•Updated May 10, 2024May 10, 2024

    • post_build_artifacts

      Public
      sw
      Other
      •0•1•0•0•Updated May 7, 2024May 7, 2024

    • testPR

      Public
      Shell
      •
      Other
      •0•0•0•0•Updated Apr 18, 2024Apr 18, 2024

    • litex_reference_designs

      Public
      Litex Reference Designs provides reference designs created out of IP Catalog using Litex integration capabilities.
      sw
      Verilog
      •
      Other
      •1•0•0•0•Updated Apr 15, 2024Apr 15, 2024

    • logic_synthesis-rs

      Public
      sw
      CMake
      •
      Other
      •1•0•0•0•Updated Feb 16, 2024Feb 16, 2024

    • testlic1

      Public
      Shell
      •
      Other
      •0•0•0•0•Updated Jan 24, 2024Jan 24, 2024

    • abc-rs

      Public
      synthesissw
      C
      •
      Other
      •0•0•2•0•Updated Jan 19, 2024Jan 19, 2024

    • axi_i2c_bridge

      Public
      hw
      SystemVerilog
      •
      Other
      •1•1•0•0•Updated Jan 16, 2024Jan 16, 2024

    • zephyr-rapidsi-dev

      Public
      embedded-sw
      C
      •
      Apache License 2.0
      •1•2•0•3•Updated Jan 16, 2024Jan 16, 2024

    • tcl

      Public
      The Tcl Core. (Mirror of core.tcl-lang.org)
      sw
      C
      •
      Other
      •187•0•0•0•Updated Jan 16, 2024Jan 16, 2024