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    70 repositories

    • verilog-pcie

      Public
      Verilog PCI express components
      Verilog
      •
      MIT License
      •314•0•0•0•Updated Jul 3, 2020Jul 3, 2020

    • opentitan

      Public
      OpenTitan: Open source silicon root of trust
      SystemVerilog
      •
      Apache License 2.0
      •805•0•0•0•Updated Jul 1, 2020Jul 1, 2020

    • platformio-core

      Public
      PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!
      Python
      •
      Apache License 2.0
      •802•0•0•0•Updated Jun 30, 2020Jun 30, 2020

    • verilog-ethernet

      Public
      Verilog Ethernet components for FPGA implementation
      Verilog
      •
      MIT License
      •719•0•0•0•Updated May 18, 2020May 18, 2020

    • 00_Image_Rotate

      Public
      视频旋转（2019FPGA大赛）
      Verilog
      •11•0•0•0•Updated May 5, 2020May 5, 2020

    • wujian100_open

      Public
      IC design and development should be faster，simpler and more reliable
      Verilog
      •
      MIT License
      •575•0•0•0•Updated Mar 23, 2020Mar 23, 2020

    • e200_opensource

      Public
      The Ultra-Low Power RISC Core
      Verilog
      •
      Apache License 2.0
      •1k•0•0•0•Updated Jan 2, 2020Jan 2, 2020

    • LeNet5

      Public
      VHDL
      •1•0•0•0•Updated Jan 1, 2020Jan 1, 2020

    • yolov2_xilinx_fpga

      Public
      A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard
      C
      •
      MIT License
      •237•0•0•0•Updated Dec 27, 2019Dec 27, 2019

    • lenet5_hls

      Public
      FPGA Accelerator for CNN using Vivado HLS
      C++
      •
      MIT License
      •92•0•0•0•Updated Nov 29, 2019Nov 29, 2019

    • Lenet_Accelerator

      Public
      A Lenet ASIC Accelerator targeting minimum number of cycles
      Verilog
      •12•0•0•0•Updated Oct 13, 2019Oct 13, 2019

    • poyo-v

      Public
      Open source RISC-V IP core for FPGA/ASIC design
      Verilog
      •
      MIT License
      •5•0•0•0•Updated Oct 12, 2019Oct 12, 2019

    • wifi_ldpc_codec

      Public
      Wi-Fi LDPC codec Verilog IP core
      Verilog
      •
      MIT License
      •9•1•0•0•Updated Oct 11, 2019Oct 11, 2019

    • daisho

      Public
      Test of the USB3 IP Core from Daisho on a Xilinx device
      Verilog
      •28•0•0•0•Updated Oct 3, 2019Oct 3, 2019

    • SD-card-controller

      Public
      WISHBONE SD Card Controller IP Core
      Verilog
      •48•1•0•0•Updated Sep 20, 2019Sep 20, 2019

    • wb2axip

      Public
      Bus bridges and other odds and ends
      Verilog
      •103•1•0•0•Updated Sep 5, 2019Sep 5, 2019

    • mor1kx

      Public
      mor1kx - an OpenRISC 1000 processor IP core
      Verilog
      •
      Other
      •147•1•0•0•Updated Aug 27, 2019Aug 27, 2019

    • ZynqMP-FPGA-Linux

      Public
      FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian9 Images (for Xilinx:Zynq Ultrascale+ MPSoC)
      Tcl
      •39•0•0•0•Updated Aug 18, 2019Aug 18, 2019

    • cores

      Public
      Various HDL (Verilog) IP Cores
      Verilog
      •215•0•0•0•Updated Aug 17, 2019Aug 17, 2019

    • SBA-Library

      Public
      SBA IP Cores http://sba.accesus.com
      VHDL
      •4•0•0•0•Updated Aug 11, 2019Aug 11, 2019

    • minist_tensorflow

      Public
      手写数字识别的实现及其lenet5原理
      Jupyter Notebook
      •1•0•0•0•Updated Jul 29, 2019Jul 29, 2019

    • LeNet5_HLS_Zynq

      Public
      LeNet5 Acceleration with HLS based FPGA Implementation
      C
      •4•0•0•0•Updated Jul 27, 2019Jul 27, 2019

    • ethernet-fmc-zynq-gem

      Public
      Example design for the Ethernet FMC using the hard GEMs of the Zynq
      Tcl
      •51•0•0•0•Updated Jul 18, 2019Jul 18, 2019

    • fp23fftk

      Public
      Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
      VHDL
      •
      GNU General Public License v3.0
      •18•0•0•0•Updated Jun 28, 2019Jun 28, 2019

    • TestCNN1

      Public
      lenet5识别车标
      Python
      •2•0•0•0•Updated Jun 23, 2019Jun 23, 2019

    • lenet5-1

      Public
      Verilog
      •
      GNU General Public License v3.0
      •2•0•0•0•Updated Jun 22, 2019Jun 22, 2019

    • FPGA-CPU-IP-Core-Verilog-Programming

      Public
      FPGA Module Mini Project Designing and Implementation of a CPU IP core with Harvard architecture using Verilog and Cyclone V Altera FPGA board , implementing the state machine of the control unit (Fetch -decode -Execute) , Memory model (Code memory and data memory ) , Assembler , I/O units (PS2 Keyboard and Graphics LCD )
      Verilog
      •1•1•0•0•Updated Jun 19, 2019Jun 19, 2019

    • AXI_digital_median_filter_IP

      Public
      An image filter IP core based on Xilinx ZYNQ SOC, Using hardware 3x3 median filter to eliminate image salt-and-pepper noise without CPU involvement. AXI4-stream interface. MIT License
      VHDL
      •
      MIT License
      •1•1•0•0•Updated May 15, 2019May 15, 2019

    • ip_repo

      Public
      Repository for Xilinx Vivado IP cores
      Verilog
      •
      MIT License
      •2•0•0•0•Updated Apr 19, 2019Apr 19, 2019

    • minist_LeNet5

      Public
      公司内部分享使用的示例
      Jupyter Notebook
      •1•0•0•0•Updated Mar 27, 2019Mar 27, 2019