Figure: Block Level Diagram of the Proposed Sleep Apnea Detection System

A typical digital hardware accelerator uses multiplyaccumulate function (MAC) as its neuron units. The synapse of the fully connected neural network multiplies its weights to the corresponding output data from the previous layer and sends it to the neuron of the next layer to get summed and either classified (at the output layer) or passed to the next layer (at the hidden layer). As a result, many multipliers need to be designed when representing the synapse of the model. When designing energy efficient hardware model, the power consumption of the system increases at a high rate due to the usage of many multipliers. To avoid this, a shifter based low-power design technique (Shift-Accumulate, SAC) has been introduced in this work where shifters have been used instead of multipliers. During the training phase of the model in software, the weights and biases were constrained in order of magnitude of 2 while maintaining the consistency of their original values.

Figure: Proposed Feedforward Neural Network Figure: Power consumption rate dreceased by 13x times when replacing multipliers with shifters Figure: Hardware Model of the Feedforward Network Figure: Simulation results on reprogrammable hardware (Nexys Artix-7 FPGA)