parameter added for primitive/verilog-implementation selection

ombhilare999 · Jul 6, 2021 · c3ea29c · c3ea29c
1 parent 13ee421
commit c3ea29c
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Showing 3 changed files with 32 additions and 26 deletions.
diff --git a/components/gpmc_to_wishbone.v b/components/gpmc_to_wishbone.v
@@ -9,8 +9,12 @@
 // Uncomment this for component simulation
 // `include "cells_sim.v"
 
-module gpmc_to_wishbone
-(
+module gpmc_to_wishbone #(
+    parameter ADDR_WIDTH = 16,      // Macro for Address  
+    parameter DATA_WIDTH = 16,      // Macro for Data
+    parameter TARGET = "ICE40"      // Target("ICE40"): ice40 primitive for tristate
+                                    // Target("GENERAL"): verilog tristate implementaion
+)(
     //System Clock and Reset
     input  wire clk,                //FPGA Clock
     input  wire reset,              //Master Reset for Wishbone Bus
@@ -34,9 +38,6 @@ module gpmc_to_wishbone
     input  wire wbm_ack         //Wishbone Acknowledge Signal from Slave
 );
 
-parameter ADDR_WIDTH = 16;      // Macro for Address  
-parameter DATA_WIDTH = 16;       // Macro for Data
-
 // Variables for the bridge
 reg  [ADDR_WIDTH-1:0] address_bridge;       
 reg  [DATA_WIDTH-1:0] write_data_bridge;
@@ -77,23 +78,26 @@ wire datacontrol;
 //                 |       |___________|
 //                 |
 //                 |---------------------------------> gpmc_latch_data
-//
-//  FPGA Primitive Implementation:
-SB_IO # (
-    .PIN_TYPE(6'b1010_01),
-    .PULLUP(1'b 0)
-) gpmc_ad_io [15:0] (
-    .PACKAGE_PIN(gpmc_ad),
-    .OUTPUT_ENABLE(!gpmc_csn1 && gpmc_advn && !gpmc_oen && gpmc_wein && reset),
-    .D_OUT_0(gpmc_latch_ad),
-    .D_IN_0(gpmc_latch_data)
-);
-///////////////////////////////////////////////////////////////////*/
+//////////////////////////////////////////////////////////////////////*/
 
-// Verilog Implementation
 assign datacontrol = (!gpmc_csn1 && gpmc_advn && !gpmc_oen && gpmc_wein && reset);
-assign gpmc_ad = datacontrol ? gpmc_latch_ad : 16'bz;
-assign gpmc_latch_data = gpmc_ad;
+
+generate 
+    if (TARGET == "ICE40") begin //  FPGA Primitive Implementation:     
+        SB_IO # (
+            .PIN_TYPE(6'b1010_01),
+            .PULLUP(1'b 0)
+        ) gpmc_ad_io [15:0] (
+            .PACKAGE_PIN(gpmc_ad),
+            .OUTPUT_ENABLE(datacontrol),
+            .D_OUT_0(gpmc_latch_ad),
+            .D_IN_0(gpmc_latch_data)
+        );
+    end else if (TARGET == "GENERAL") begin    // Verilog Implementation
+        assign gpmc_ad = datacontrol ? gpmc_latch_ad : 16'bz;
+        assign gpmc_latch_data = gpmc_ad;   
+    end
+endgenerate
 
 initial begin
     address_bridge <= 5'b00000;

diff --git a/examples/arm_blink_leds/leds_wb.v b/examples/arm_blink_leds/leds_wb.v
@@ -6,8 +6,10 @@
 
 `default_nettype none
 
-module leds_wb
-(
+module leds_wb #(
+	parameter ADDR_WIDTH = 1,   // Parameters for Address and Data
+	parameter DATA_WIDTH = 16
+)(
     // Clock and Reset
 	input  wire clk,
 	input  wire reset,
@@ -24,9 +26,7 @@ module leds_wb
 	output wire wbs_ack        //Wishbone Acknowledge Signal from Slave
 );
 
-// Parameters for Address and Data
-parameter ADDR_WIDTH = 1;
-parameter DATA_WIDTH = 16;
+
 
 reg [3:0] mem;
 reg [3:0] wbs_readdata_reg;

diff --git a/examples/arm_blink_leds/top.v b/examples/arm_blink_leds/top.v
@@ -53,7 +53,9 @@ assign reset = 1'b1;     //Active Low Signal
 
 gpmc_to_wishbone # (
     .ADDR_WIDTH(ADDR_WIDTH),      // Macro for Address  
-    .DATA_WIDTH(DATA_WIDTH)       // Macro for Data
+    .DATA_WIDTH(DATA_WIDTH),      // Macro for Data
+    .TARGET("ICE40")              // Target("ICE40")   fpga prmitive
+                                  // Target("GENERAL") verilog implementaion
 ) wb_controller (
     //System Clock and Reset
     .clk(clk),                    //FPGA Clock