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Merge pull request WebAssembly#515 from WebAssembly/refactor.spec
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[spec] Refactor spec to align with interpreter
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@rossberg
rossberg authored Sep 8, 2021
2 parents 02cf939 + a288cc7 commit b9fbe20
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140 changes: 70 additions & 70 deletions document/core/appendix/gen-index-instructions.py
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140 changes: 70 additions & 70 deletions document/core/appendix/index-instructions.rst
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4 changes: 2 additions & 2 deletions document/core/appendix/index-types.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -12,8 +12,8 @@ Category Constructor
:ref:`Number type <syntax-numtype>` |I64| :math:`\hex{7E}` (-2 as |Bs7|)
:ref:`Number type <syntax-numtype>` |F32| :math:`\hex{7D}` (-3 as |Bs7|)
:ref:`Number type <syntax-numtype>` |F64| :math:`\hex{7C}` (-4 as |Bs7|)
:ref:`Number type <syntax-numtype>` |V128| :math:`\hex{7B}` (-5 as |Bs7|)
(reserved) :math:`\hex{7B}` .. :math:`\hex{71}`
:ref:`Number type <syntax-vectype>` |V128| :math:`\hex{7B}` (-5 as |Bs7|)
(reserved) :math:`\hex{7A}` .. :math:`\hex{71}`
:ref:`Reference type <syntax-reftype>` |FUNCREF| :math:`\hex{70}` (-16 as |Bs7|)
:ref:`Reference type <syntax-reftype>` |EXTERNREF| :math:`\hex{6F}` (-17 as |Bs7|)
(reserved) :math:`\hex{6E}` .. :math:`\hex{61}`
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44 changes: 22 additions & 22 deletions document/core/binary/instructions.rst
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Expand Up @@ -461,17 +461,17 @@ whereas the actual opcode is encoded by a variable-length :ref:`unsigned integer
\end{array}
.. index:: simd instruction
.. index:: vector instruction
pair: binary format; instruction
.. _binary-instr-simd:
.. _binary-instr-vec:

SIMD Instructions
~~~~~~~~~~~~~~~~~~~~
Vector Instructions
~~~~~~~~~~~~~~~~~~~

All variants of :ref:`SIMD instructions <syntax-instr-simd>` are represented by separate byte codes.
All variants of :ref:`vector instructions <syntax-instr-vec>` are represented by separate byte codes.
They all have a one byte prefix, whereas the actual opcode is encoded by a variable-length :ref:`unsigned integer <binary-uint>`.

SIMD loads and stores are followed by the encoding of their |memarg| immediate.
Vector loads and stores are followed by the encoding of their |memarg| immediate.

.. _binary-laneidx:

Expand Down Expand Up @@ -544,11 +544,11 @@ The |SHUFFLE| instruction is also followed by the encoding of 16 |laneidx| immed
\hex{FD}~~34{:}\Bu32~~l{:}\Blaneidx &\Rightarrow& \F64X2.\REPLACELANE~l \\
\end{array}
All other SIMD instructions are plain opcodes without any immediates.
All other vector instructions are plain opcodes without any immediates.

.. math::
\begin{array}{llclll}
\production{instruction} & \Binstr &::=& \dots && \phantom{simdhaslongerinstructionnames} \\&&|&
\production{instruction} & \Binstr &::=& \dots && \phantom{vechaslongerinstructionnames} \\&&|&
\hex{FD}~~14{:}\Bu32 &\Rightarrow& \I8X16.\SWIZZLE \\ &&|&
\hex{FD}~~15{:}\Bu32 &\Rightarrow& \I8X16.\SPLAT \\ &&|&
\hex{FD}~~16{:}\Bu32 &\Rightarrow& \I16X8.\SPLAT \\ &&|&
Expand All @@ -562,7 +562,7 @@ All other SIMD instructions are plain opcodes without any immediates.

.. math::
\begin{array}{llclll}
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
\hex{FD}~~35{:}\Bu32 &\Rightarrow& \I8X16.\VEQ \\ &&|&
\hex{FD}~~36{:}\Bu32 &\Rightarrow& \I8X16.\VNE \\ &&|&
\hex{FD}~~37{:}\Bu32 &\Rightarrow& \I8X16.\VLT\K{\_s} \\ &&|&
Expand All @@ -577,7 +577,7 @@ All other SIMD instructions are plain opcodes without any immediates.
.. math::
\begin{array}{llclll}
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
\hex{FD}~~45{:}\Bu32 &\Rightarrow& \I16X8.\VEQ \\ &&|&
\hex{FD}~~46{:}\Bu32 &\Rightarrow& \I16X8.\VNE \\ &&|&
\hex{FD}~~47{:}\Bu32 &\Rightarrow& \I16X8.\VLT\K{\_s} \\ &&|&
Expand All @@ -592,7 +592,7 @@ All other SIMD instructions are plain opcodes without any immediates.
.. math::
\begin{array}{llclll}
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
\hex{FD}~~55{:}\Bu32 &\Rightarrow& \I32X4.\VEQ \\ &&|&
\hex{FD}~~56{:}\Bu32 &\Rightarrow& \I32X4.\VNE \\ &&|&
\hex{FD}~~57{:}\Bu32 &\Rightarrow& \I32X4.\VLT\K{\_s} \\ &&|&
Expand All @@ -607,7 +607,7 @@ All other SIMD instructions are plain opcodes without any immediates.
.. math::
\begin{array}{llclll}
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
\hex{FD}~~214{:}\Bu32 &\Rightarrow& \I64X2.\VEQ \\ &&|&
\hex{FD}~~215{:}\Bu32 &\Rightarrow& \I64X2.\VNE \\ &&|&
\hex{FD}~~216{:}\Bu32 &\Rightarrow& \I64X2.\VLT\K{\_s} \\ &&|&
Expand All @@ -620,7 +620,7 @@ All other SIMD instructions are plain opcodes without any immediates.

.. math::
\begin{array}{llclll}
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
\hex{FD}~~65{:}\Bu32 &\Rightarrow& \F32X4.\VEQ \\ &&|&
\hex{FD}~~66{:}\Bu32 &\Rightarrow& \F32X4.\VNE \\ &&|&
\hex{FD}~~67{:}\Bu32 &\Rightarrow& \F32X4.\VLT \\ &&|&
Expand All @@ -631,7 +631,7 @@ All other SIMD instructions are plain opcodes without any immediates.
.. math::
\begin{array}{llclll}
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
\hex{FD}~~71{:}\Bu32 &\Rightarrow& \F64X2.\VEQ \\ &&|&
\hex{FD}~~72{:}\Bu32 &\Rightarrow& \F64X2.\VNE \\ &&|&
\hex{FD}~~73{:}\Bu32 &\Rightarrow& \F64X2.\VLT \\ &&|&
Expand All @@ -646,7 +646,7 @@ All other SIMD instructions are plain opcodes without any immediates.

.. math::
\begin{array}{llclll}
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
\hex{FD}~~77{:}\Bu32 &\Rightarrow& \V128.\VNOT \\ &&|&
\hex{FD}~~78{:}\Bu32 &\Rightarrow& \V128.\VAND \\ &&|&
\hex{FD}~~79{:}\Bu32 &\Rightarrow& \V128.\VANDNOT \\ &&|&
Expand All @@ -665,7 +665,7 @@ All other SIMD instructions are plain opcodes without any immediates.

.. math::
\begin{array}{llclll}
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
\hex{FD}~~96{:}\Bu32 &\Rightarrow& \I8X16.\VABS \\ &&|&
\hex{FD}~~97{:}\Bu32 &\Rightarrow& \I8X16.\VNEG \\ &&|&
\hex{FD}~~98{:}\Bu32 &\Rightarrow& \I8X16.\VPOPCNT \\ &&|&
Expand All @@ -691,7 +691,7 @@ All other SIMD instructions are plain opcodes without any immediates.
.. math::
\begin{array}{llclll}
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
\hex{FD}~~124{:}\Bu32 &\Rightarrow& \I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}\\ &&|&
\hex{FD}~~125{:}\Bu32 &\Rightarrow& \I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}\\ &&|&
\hex{FD}~~128{:}\Bu32 &\Rightarrow& \I16X8.\VABS \\ &&|&
Expand Down Expand Up @@ -728,7 +728,7 @@ All other SIMD instructions are plain opcodes without any immediates.
.. math::
\begin{array}{llclll}
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
\hex{FD}~~126{:}\Bu32 &\Rightarrow& \I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}\\ &&|&
\hex{FD}~~127{:}\Bu32 &\Rightarrow& \I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}\\ &&|&
\hex{FD}~~160{:}\Bu32 &\Rightarrow& \I32X4.\VABS \\ &&|&
Expand Down Expand Up @@ -758,7 +758,7 @@ All other SIMD instructions are plain opcodes without any immediates.
.. math::
\begin{array}{llclll}
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
\hex{FD}~~192{:}\Bu32 &\Rightarrow& \I64X2.\VABS \\ &&|&
\hex{FD}~~193{:}\Bu32 &\Rightarrow& \I64X2.\VNEG \\ &&|&
\hex{FD}~~195{:}\Bu32 &\Rightarrow& \I64X2.\ALLTRUE \\ &&|&
Expand All @@ -784,7 +784,7 @@ All other SIMD instructions are plain opcodes without any immediates.

.. math::
\begin{array}{llclll}
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
\hex{FD}~~103{:}\Bu32 &\Rightarrow& \F32X4.\VCEIL \\ &&|&
\hex{FD}~~104{:}\Bu32 &\Rightarrow& \F32X4.\VFLOOR \\ &&|&
\hex{FD}~~105{:}\Bu32 &\Rightarrow& \F32X4.\VTRUNC \\ &&|&
Expand All @@ -804,7 +804,7 @@ All other SIMD instructions are plain opcodes without any immediates.
.. math::
\begin{array}{llclll}
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
\hex{FD}~~116{:}\Bu32 &\Rightarrow& \F64X2.\VCEIL \\ &&|&
\hex{FD}~~117{:}\Bu32 &\Rightarrow& \F64X2.\VFLOOR \\ &&|&
\hex{FD}~~122{:}\Bu32 &\Rightarrow& \F64X2.\VTRUNC \\ &&|&
Expand All @@ -824,7 +824,7 @@ All other SIMD instructions are plain opcodes without any immediates.
.. math::
\begin{array}{llclll}
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
\hex{FD}~~248{:}\Bu32 &\Rightarrow& \I32X4.\TRUNC\K{\_sat\_f32x4\_s} \\ &&|&
\hex{FD}~~249{:}\Bu32 &\Rightarrow& \I32X4.\TRUNC\K{\_sat\_f32x4\_u} \\ &&|&
\hex{FD}~~250{:}\Bu32 &\Rightarrow& \F32X4.\CONVERT\K{\_i32x4\_s} \\ &&|&
Expand Down
17 changes: 16 additions & 1 deletion document/core/binary/types.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,22 @@ Number Types
\hex{7F} &\Rightarrow& \I32 \\ &&|&
\hex{7E} &\Rightarrow& \I64 \\ &&|&
\hex{7D} &\Rightarrow& \F32 \\ &&|&
\hex{7C} &\Rightarrow& \F64 \\ &&|&
\hex{7C} &\Rightarrow& \F64 \\
\end{array}
.. index:: vector type
pair: binary format; vector type
.. _binary-vectype:

Vector Types
~~~~~~~~~~~~

:ref:`Vector types <syntax-vectype>` are also encoded by a single byte.

.. math::
\begin{array}{llclll@{\qquad\qquad}l}
\production{vector type} & \Bvectype &::=&
\hex{7B} &\Rightarrow& \V128 \\
\end{array}
Expand Down
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