Any good, modern ISA should have a fused multiply-accumulate instruction.

We could add four 3-operand instructions:

Some ISA:s have more flexibility in selecting the output register:

• RISC-V has a special four-operand instruction encoding for FMADD, to freely select the output register.
• Likewise, early AMD x86 AVX had FMA4 with four operands. That instruction is no longer supported in newer CPU:s though.
• The Intel/AMD x86 AVX ISA has FMA3 with three operands, but three variants that effectively allow the selection of which of the three registers to use as an output register.
• ARM (VFPv4/NEONv2) has a three-operand FMA.