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Commits on Feb 22, 2023

• minerva: fix Amaranth documentation URL.

  jfng

  committed
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• minerva: add MINERVA_WITH_{I,D}CACHE defines.

  jfng

  committed
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• minerva: nMigen was renamed to Amaranth HDL.

  jfng

  committed
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Commits on Feb 21, 2023

• minerva: add README.

  

  Jean-François Nguyen

  authored and

  jfng

  committed
  0d71e77

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• Add minerva core

  

  Jean-François Nguyen

  authored and

  jfng

  committed
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Commits on Feb 13, 2023

• Update to latest GH action

  mmicko

  authored
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Commits on Oct 24, 2022

• Update CI script

  mmicko

  authored
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Commits on Sep 12, 2022

• Nightly build

  mmicko

  authored
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Commits on May 13, 2022

• Add nerv tests to CI

  mmicko

  committed
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• Add GitHub Action

  mmicko

  committed
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Commits on May 12, 2022

• Update quickstart.md

  clairexen

  authored
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• Update quickstart.md

  clairexen

  authored
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• Add abspath option

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  clairexen

  committed
  ef7600c

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• Merge pull request YosysHQ#1 from WeeBull/patch-1

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  clairexen

  authored
  26aedc0

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• Merge pull request YosysHQ#3 from YosysHQ/csr

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  clairexen

  authored
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• Merge branch 'csr_improvements' of github.com:YosysHQ/riscv-formal into csr

  clairexen

  committed
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Commits on Apr 25, 2022

• Call sby with full sby path name

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  clairexen

  committed
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Commits on Apr 6, 2022

• Update to latest VexRiscv, with fix reapplied

  mmicko

  committed
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Commits on Apr 4, 2022

• Fix building with or without Verific and latest yosys

  mmicko

  committed
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Commits on Mar 18, 2022

• Fixed a link

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  clairexen

  committed
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Commits on Mar 11, 2022

• Update the link to the presentation slides

  WeeBull

  authored
  a6bd320

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Commits on Dec 16, 2021

• More email and links updates

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  clairexen

  committed
  e10f8c1

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• Update emails and links

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  clairexen

  committed
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Commits on Dec 15, 2021

• Silence another "right shift count >= width of value" verific warning

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  clairexen

  committed
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Commits on Dec 13, 2021

• Add M-Mode CSRs to rvfi_macros, Add RVFI_CONN32 macro

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  clairexen

  committed
  bf46c35

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• Fix name in copyright headers

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  clairexen

  committed
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• Silence verific warning "right shift count >= width of value"

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  clairexen

  committed
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• Fix rvfi_testbench for Verific parser

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  clairexen

  committed
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Commits on Dec 10, 2021

• Fix Verilog pre-processor usage in rvfi_csrw_check

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  clairexen

  committed
  1e8698c

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• Fix rand const reg issue

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  clairexen

  committed
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Commits on Dec 9, 2021

• Add [verilog-files] and [vhdl-files] cfg sections

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  clairexen

  committed
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Commits on Nov 26, 2021

• Add missing RISCV_FORMAL_UMODE to picorv32 example

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  clairexen

  committed
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Commits on Oct 12, 2020

• Hot fix pre-compiled VexRiscv.v for current RVFI spec

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  clairexen

  committed
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Commits on May 15, 2020

• Add check groups, add assume enable/disable regex pattern

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  clairexen

  committed
  03501a0

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Commits on May 12, 2020

• Fix cover check, add cover to picorv32 example

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  clairexen

  committed
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