driver: reset: Add Mango(SG2042) SOC reset driver

milkv-pioneer · Mar 4, 2024 · 2584b9d · 2584b9d
1 parent cb313e7
commit 2584b9d
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diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
@@ -41,3 +41,4 @@ obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
 obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o
 obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
 obj-$(CONFIG_ARCH_ZYNQMP) += reset-zynqmp.o
+obj-$(CONFIG_SOC_SOPHGO) += reset-sophgo.o
diff --git a/drivers/reset/reset-sophgo.c b/drivers/reset/reset-sophgo.c
@@ -0,0 +1,163 @@
+/*
+ * Sophgo SoCs Reset Controller driver
+ *
+ * Copyright (c) 2018 Bitmain Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/of_device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+
+#define BITS_PER_REG	32
+
+struct bm_reset_data {
+	spinlock_t			lock;
+	void __iomem			*membase;
+	struct reset_controller_dev	rcdev;
+	struct regmap		*syscon_rst;
+	u32			top_rst_offset;
+};
+
+static int bm_reset_assert(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	struct bm_reset_data *data = container_of(rcdev,
+						     struct bm_reset_data,
+						     rcdev);
+	int bank = id / BITS_PER_REG;
+	int offset = id % BITS_PER_REG;
+	unsigned long flags;
+	u32 reg;
+
+	spin_lock_irqsave(&data->lock, flags);
+
+	regmap_read(data->syscon_rst, data->top_rst_offset + (bank * 4),
+		&reg);
+	regmap_write(data->syscon_rst, data->top_rst_offset + (bank * 4),
+		reg & ~BIT(offset));
+
+	spin_unlock_irqrestore(&data->lock, flags);
+
+	return 0;
+}
+
+static int bm_reset_deassert(struct reset_controller_dev *rcdev,
+				unsigned long id)
+{
+	struct bm_reset_data *data = container_of(rcdev,
+						     struct bm_reset_data,
+						     rcdev);
+	int bank = id / BITS_PER_REG;
+	int offset = id % BITS_PER_REG;
+	unsigned long flags;
+	u32 reg;
+
+	spin_lock_irqsave(&data->lock, flags);
+
+	regmap_read(data->syscon_rst, data->top_rst_offset + (bank * 4),
+		&reg);
+	regmap_write(data->syscon_rst,  data->top_rst_offset + (bank * 4),
+		reg | BIT(offset));
+
+	spin_unlock_irqrestore(&data->lock, flags);
+
+	return 0;
+}
+
+static const struct reset_control_ops bm_reset_ops = {
+	.assert		= bm_reset_assert,
+	.deassert	= bm_reset_deassert,
+};
+
+static const struct of_device_id bm_reset_dt_ids[] = {
+	 { .compatible = "bitmain,reset", },
+	 { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, bm_reset_dt_ids);
+
+static int bm_reset_probe(struct platform_device *pdev)
+{
+	struct bm_reset_data *data;
+	int ret = 0;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node, *np_top;
+	static struct regmap *syscon;
+
+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	np_top = of_parse_phandle(np, "subctrl-syscon", 0);
+	if (!np_top) {
+		dev_err(dev, "%s can't get subctrl-syscon node\n", __func__);
+		goto out_free_devm;
+	}
+
+	syscon = syscon_node_to_regmap(np_top);
+	if (IS_ERR(syscon)) {
+		dev_err(dev, "cannot get regmap\n");
+		goto out_free_devm;
+	}
+
+	data->syscon_rst = syscon;
+	ret = device_property_read_u32(&pdev->dev, "top_rst_offset",
+		&data->top_rst_offset);
+	if (ret < 0) {
+		dev_err(dev, "cannot get top_rst_offset\n");
+		goto out_free_devm;
+	}
+
+	ret = device_property_read_u32(&pdev->dev, "nr_resets",
+		&data->rcdev.nr_resets);
+	if (ret < 0) {
+		dev_err(dev, "cannot get nr_resets\n");
+		goto out_free_devm;
+	}
+
+	spin_lock_init(&data->lock);
+
+	data->rcdev.owner = THIS_MODULE;
+	data->rcdev.ops = &bm_reset_ops;
+	data->rcdev.of_node = pdev->dev.of_node;
+
+	ret = devm_reset_controller_register(&pdev->dev, &data->rcdev);
+	if (!ret)
+		return 0;
+
+out_free_devm:
+	devm_kfree(&pdev->dev, data);
+	return ret;
+}
+
+static struct platform_driver bm_reset_driver = {
+	.probe	= bm_reset_probe,
+	.driver = {
+		.name		= "bm-reset",
+		.of_match_table	= bm_reset_dt_ids,
+	},
+};
+
+static int __init bm_reset_init(void)
+{
+	return platform_driver_register(&bm_reset_driver);
+}
+postcore_initcall(bm_reset_init);
+
+MODULE_AUTHOR("Wei Huang<wei.huang01@bitmain.com>");
+MODULE_DESCRIPTION("Bitmain SoC Reset Controoler Driver");
+MODULE_LICENSE("GPL");
diff --git a/include/dt-bindings/reset/sophgo-mango-resets.h b/include/dt-bindings/reset/sophgo-mango-resets.h
@@ -0,0 +1,96 @@
+/*
+ * Sophgo SoCs Reset definitions
+ *
+ * Copyright (c) 2018 Bitmain Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _DT_BINDINGS_RST_MANGO_H_
+#define _DT_BINDINGS_RST_MANGO_H_
+
+#define RST_MAIN_AP                            0
+#define RST_RISCV_CPU                          1
+#define RST_RISCV_LOW_SPEED_LOGIC              2
+#define RST_RISCV_CMN                          3
+#define RST_HSDMA                              4
+#define RST_SYSDMA                             5
+#define RST_EFUSE0                             6
+#define RST_EFUSE1                             7
+#define RST_RTC                                8
+#define RST_TIMER                              9
+#define RST_WDT                                10
+#define RST_AHB_ROM0                           11
+#define RST_AHB_ROM1                           12
+#define RST_I2C0                               13
+#define RST_I2C1                               14
+#define RST_I2C2                               15
+#define RST_I2C3                               16
+#define RST_GPIO0                              17
+#define RST_GPIO1                              18
+#define RST_GPIO2                              19
+#define RST_PWM                                20
+#define RST_AXI_SRAM0                          21
+#define RST_AXI_SRAM1                          22
+#define RST_SF0                                23
+#define RST_SF1                                24
+#define RST_LPC                                25
+#define RST_ETH0                               26
+#define RST_EMMC                               27
+#define RST_SD                                 28
+#define RST_UART0                              29
+#define RST_UART1                              30
+#define RST_UART2                              31
+
+#define RST_UART3                              32
+#define RST_SPI0                               33
+#define RST_SPI1                               34
+#define RST_DBG_I2C                            35
+#define RST_PCIE0                              36
+#define RST_PCIE1                              37
+#define RST_DDR0                               38
+#define RST_DDR1                               39
+#define RST_DDR2                               40
+#define RST_DDR3                               41
+#define RST_FAU0                               42
+#define RST_FAU1                               43
+#define RST_FAU2                               44
+#define RST_RXU0                               45
+#define RST_RXU1                               46
+#define RST_RXU2                               47
+#define RST_RXU3                               48
+#define RST_RXU4                               49
+#define RST_RXU5                               50
+#define RST_RXU6                               51
+#define RST_RXU7                               52
+#define RST_RXU8                               53
+#define RST_RXU9                               54
+#define RST_RXU10                              55
+#define RST_RXU11                              56
+#define RST_RXU12                              57
+#define RST_RXU13                              58
+#define RST_RXU14                              59
+#define RST_RXU15                              60
+#define RST_RXU16                              61
+#define RST_RXU17                              62
+#define RST_RXU18                              63
+#define RST_RXU19                              64
+#define RST_RXU20                              65
+#define RST_RXU21                              66
+#define RST_RXU22                              67
+#define RST_RXU23                              68
+#define RST_RXU24                              69
+#define RST_RXU25                              70
+#define RST_RXU26                              71
+#define RST_RXU27                              72
+#define RST_RXU28                              73
+#define RST_RXU29                              74
+#define RST_RXU30                              75
+#define RST_RXU31                              76
+
+#define RST_MAX_NUM  (RST_RXU31+1)
+
+#endif