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Add arm64 support for vector instructions
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Theodore Dubois committed May 4, 2020
1 parent d5de7ad commit 81912c6
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Showing 2 changed files with 55 additions and 16 deletions.
61 changes: 55 additions & 6 deletions jit/gadgets-aarch64/misc.S
Original file line number Diff line number Diff line change
Expand Up @@ -187,15 +187,64 @@ do_helper 2
do_helper write, \size
.endr

# sync with enum vec_arg
#define VEC_ARG_LIST xmm,reg
.macro do_vec_helper rm, size=
.gadget vec_helper_\rm\size
.ifin(\rm, read,write)
\rm\()_prep (\size), vec_helper_\rm\size
.endifin
save_regs
save_c
mov x0, _cpu

# r/m argument, first
.ifin(\rm, reg)
ldrb w1, [_ip, 9]
add x1, x0, x1
.endifin
.ifin(\rm, read,write)
mov x1, _xaddr
.endifin
.ifin(\rm, imm)
ldrh w1, [_ip, 9]
.endifin

# reg argument, second
.ifin(\rm, read,write)
ldr x2, [_ip, 16]
add x2, x0, x2
ldr x8, [_ip, 8]
.endifin
.ifin(\rm, reg,imm)
ldr x2, [_ip, 8]
add x2, x0, x2
ldr x8, [_ip]
.endifin
blr x8

# important: this is VEC_ARG_LIST^2
.gadget_list vec_helper_reg, xmm_xmm,xmm_reg,reg_xmm,reg_reg
restore_c
load_regs
.ifc \rm,write
write_done (\size), vec_helper_\rm\size
.endif
.ifin(\rm, reg,imm)
gret 2
.endifin
.ifin(\rm, read,write)
gret 3
.endifin
.ifc \rm,read
read_bullshit (\size), vec_helper_\rm\size
.else N .ifc \rm,write
write_bullshit (\size), vec_helper_\rm\size
.endif N .endif
.endm

.irp rm, reg,imm
do_vec_helper \rm
.endr
.irp size, SIZE_LIST,64,128
.gadget_list vec_helper_load\size\(), VEC_ARG_LIST
.gadget_list vec_helper_store\size\(), VEC_ARG_LIST
do_vec_helper read, \size
do_vec_helper write, \size
.endr

.gadget fstsw_ax
Expand Down
10 changes: 0 additions & 10 deletions jit/gadgets-x86_64/misc.S
Original file line number Diff line number Diff line change
Expand Up @@ -137,9 +137,6 @@ do_helper 2
do_helper write, \size
.endr

# sync with enum vec_arg
#define VEC_ARG_LIST reg,imm

.macro do_vec_helper rm, size=
.gadget vec_helper_\rm\size
.ifin(\rm, read,write)
Expand Down Expand Up @@ -190,18 +187,11 @@ do_helper 2
.irp rm, reg,imm
do_vec_helper \rm
.endr
.gadget_list vec_helper, reg,imm

.irp size, SIZE_LIST,64,128
do_vec_helper read, \size
do_vec_helper write, \size
.endr

# vec_helper_reg(reg, reg2): helper(&reg, &reg2)
# vec_helper_imm(imm, reg): helper(imm, &reg)
# vec_helper_read128(addr, reg): helper(addr, &reg)
# vec_helper_write128(addr, reg): helper(addr, &reg)

.gadget fstsw_ax
movw CPU_fsw(%_cpu), %ax
gret

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