0.6 hs laid out, USB cleanup + PDN checks TODO

joshajohnson · Aug 16, 2020 · fb3d160 · fb3d160
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commit fb3d160
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diff --git a/Documents/imgs/assembly-instructions/led_cut.jpg b/Documents/imgs/assembly-instructions/led_cut.jpg
diff --git a/Documents/imgs/assembly-instructions/step-3.jpg b/Documents/imgs/assembly-instructions/step-3.jpg
diff --git a/Documents/imgs/assembly-instructions/step-5-1.jpg b/Documents/imgs/assembly-instructions/step-5-1.jpg
diff --git a/Documents/imgs/assembly-instructions/step-5-2.jpg b/Documents/imgs/assembly-instructions/step-5-2.jpg
diff --git a/Documents/imgs/assembly-instructions/step-5-3.jpg b/Documents/imgs/assembly-instructions/step-5-3.jpg
diff --git a/Documents/imgs/assembly-instructions/step-6-1.jpg b/Documents/imgs/assembly-instructions/step-6-1.jpg
diff --git a/Documents/imgs/assembly-instructions/step-6-3.jpg b/Documents/imgs/assembly-instructions/step-6-3.jpg
diff --git a/Hardware/0.6-hs/Hub16-cache.lib b/Hardware/0.6-hs/Hub16-cache.lib
diff --git a/Hardware/0.6-hs/Hub16.kicad_pcb b/Hardware/0.6-hs/Hub16.kicad_pcb
diff --git a/Hardware/0.6-hs/Hub16.pro b/Hardware/0.6-hs/Hub16.pro
@@ -0,0 +1,264 @@
+update=Wed 12 Aug 2020 22:18:25
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=./
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=Pcbnew
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=Hub16.net
+CopperLayerCount=2
+BoardThickness=1.6
+AllowMicroVias=0
+AllowBlindVias=0
+RequireCourtyardDefinitions=0
+ProhibitOverlappingCourtyards=1
+MinTrackWidth=0.2
+MinViaDiameter=0.6
+MinViaDrill=0.3
+MinMicroViaDiameter=0.2
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+TrackWidth4=0.5
+ViaDiameter1=0.6
+ViaDrill1=0.3
+ViaDiameter2=0.6
+ViaDrill2=0.3
+dPairWidth1=0.2
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+OthersTextUpright=1
+SolderMaskClearance=0
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+[pcbnew/Layer.F.Cu]
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+[pcbnew/Layer.In21.Cu]
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+Name=In22.Cu
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+[pcbnew/Layer.In26.Cu]
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+[pcbnew/Layer.In30.Cu]
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+[pcbnew/Layer.F.Fab]
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+[pcbnew/Layer.Rescue]
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+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
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+TrackWidth=0.25
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+[pcbnew/Netclasses/1]
+Name=Power
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+dPairViaGap=0.25