minor clean

jmacd · jmacd · May 1, 2024 · Mar 4, 2024 · Mar 4, 2024 · Mar 7, 2024
commit 6ac000408d32bc1458d9515d9bb681cb92529287
diff --git a/examples/pwm_outin/pwm_outin.c b/examples/pwm_outin/pwm_outin.c
@@ -37,33 +37,14 @@ void runBlue(ThreadID tid, Args args) {
   gpio_pin pin = GPIO_PIN(P9_12);
 
   PRULOG_1u32(INFO, "starting reader %uns", PERIOD / 2);
-  // PWM_ClearInterrupt();
 
   Timestamp clock;
   ReadClock(&clock);
   while (1) {
     uint32_t value = GPIO_GetPin(pin);
+    uint32_t tbcnt = PWMSS1.EPWM_TBCNT;
 
-    // uint32_t val1 = PWMSS1.EPWM_TBCNT;
-    // uint32_t val2 = PWMSS1.EPWM_ETPS;
-    // uint32_t val2 = PWMSS1.EPWM_ETFLG;
-    // uint32_t val2 = PWMSS1.EPWM_ETSEL;
-    // uint32_t val2 = PWMSS1.EPWM_CMPB;
-    // uint32_t val2 = EDMA_BASE[SHADOW1(EDMAREG_SERH)];
-    uint32_t val1;
-    uint32_t val2;
-
-    val1 = PWMSS1.EPWM_TBCNT;
-    val2 = PWMSS1.EPWM_ETFLG;
-
-    PRULOG_2u32(INFO_NOYIELD, "tbcntx(b) %u etflg %u", val1, val2);
-
-    // PWM_ClearInterrupt();
-
-    val1 = PWMSS1.EPWM_TBCNT;
-    val2 = PWMSS1.EPWM_ETFLG;
-
-    PRULOG_2u32(INFO_NOYIELD, "tbcnt(a) %u etflg %u", val1, val2);
+    PRULOG_2u32(INFO_NOYIELD, "read value %u tbcnt %u", value, tbcnt);
 
     SleepUntil(&clock, PERIOD / 2);
   }
@@ -91,18 +72,8 @@ int main(void) {
 
   PWM_ClearInterrupt();
 
-  int32_t flag = PWMSS1.EPWM_ETFLG;
-  int32_t clk = PWMSS1.EPWM_TBCNT;
-
-  PRULOG_2u32(INFO_NOYIELD, "about to enable %u %u", flag, clk);
-
   PWM_Enable();
 
-  flag = PWMSS1.EPWM_ETFLG;
-  clk = PWMSS1.EPWM_TBCNT;
-  PRULOG_2u32(INFO_NOYIELD, "now enabled %u %u", flag, clk);
-
-  // @@@ TODO/Note: this call has to be added in other tests, following PWM_Enable, examples...
   ControllerEnable();
 
   return Run();

diff --git a/lib/intc/am335x/intc.c b/lib/intc/am335x/intc.c
@@ -36,13 +36,6 @@ void ControllerInit(void) {
   // this PRU will use.
   CT_INTC.SECR0 = 0xffffffff;
   CT_INTC.SECR1 = 0xffffffff;
-
-  // Unset the raw events
-  // CT_INTC.SICR_bit.STS_CLR_IDX = ARM_TO_PRU_EVT;
-  // CT_INTC.SICR_bit.STS_CLR_IDX = SYSEVT_PR1_IEP_TIM_CAP_CMP_PEND;
-  // CT_INTC.SICR_bit.STS_CLR_IDX = SYSEVT_EPWM1_INTR_PEND;
-
-  // CT_INTC.HIER_bit.EN_HINT |= 8;
 }
 
 void InterruptHandlerInit(uint8_t evt, InterruptHandler *handler) {

diff --git a/lib/pwm/am335x/epwm1_intr_pend.yaml b/lib/pwm/am335x/epwm1_intr_pend.yaml
@@ -2,6 +2,3 @@ incoming:
 - event: SYSEVT_TPCC_INT_PEND_PO1
   channel: 5
   desc: EDMA interrupt routed from ePWM module 1
-- event: SYSEVT_EPWM1_INTR_PEND
-  channel: 4
-  desc: eHRPWM interrupt from ePWM module 1 (not routed?)
diff --git a/lib/pwm/am335x/pwm-am335x.c b/lib/pwm/am335x/pwm-am335x.c
@@ -225,14 +225,10 @@ void PWM_Enable(void) {
   // PWM_BASE.SYSCONFIG_bit.IDLEMODE = 2;
   PWM_BASE.EPWM_TBCTL |= (3 << 14); // FREE_SOFT: Free run
 
-  // //////////////////////////////////////////////////////////////////////
-  // // Control module
-  // CONTROL_MODULE[0x664 / WORDSZ] = (1 << 1); // Enable TBCLK for EPWM1
+  //////////////////////////////////////////////////////////////////////
+  // Control module
+  CONTROL_MODULE[0x664 / WORDSZ] = (1 << 1); // Enable TBCLK for EPWM1
 
   PWM_BASE.EPWM_ETSEL = (1 << 3) | // Interrupts enabled
                         (6 << 0);  // Interrupt on CMB-B == TBCNT
 }
-
-// @4a320204: SRSR1 = 40000000
-// TODO: This looks like event 62, which is tpcc_errint_pend_po
-// so possible EDMA is still the problem