topology: add a "core" parameter to the W_EQ_IIR() macro

This places all SectionWidget.EQIIR* topology widgets, created by the W_EQ_IIR() macro on the same core, on which the respective pipeline is scheduled. Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
iganakov · Apr 8, 2020 · 8821c1c · 8821c1c
1 parent 40e68e2
commit 8821c1c
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Showing 9 changed files with 18 additions and 11 deletions.
diff --git a/tools/topology/m4/eq_iir.m4 b/tools/topology/m4/eq_iir.m4
@@ -2,16 +2,17 @@ divert(-1)
 
 dnl Define macro for Eq effect widget
 
-dnl EQ name)
+dnl N_EQ_IIR(name)
 define(`N_EQ_IIR', `EQIIR'PIPELINE_ID`.'$1)
 
-dnl W_EQ(name, format, periods_sink, periods_source, kcontrols_list)
+dnl W_EQ(name, format, periods_sink, periods_source, core, kcontrols_list)
 define(`W_EQ_IIR',
 `SectionVendorTuples."'N_EQ_IIR($1)`_tuples_w" {'
 `	tokens "sof_comp_tokens"'
 `	tuples."word" {'
 `		SOF_TKN_COMP_PERIOD_SINK_COUNT'		STR($3)
 `		SOF_TKN_COMP_PERIOD_SOURCE_COUNT'	STR($4)
+`		SOF_TKN_COMP_CORE_ID'			STR($5)
 `	}'
 `}'
 `SectionData."'N_EQ_IIR($1)`_data_w" {'
@@ -45,7 +46,7 @@ define(`W_EQ_IIR',
 `		"'N_EQ_IIR($1)`_data_str_type"'
 `	]'
 `	bytes ['
-		$5
+		$6
 `	]'
 `}')
 

diff --git a/tools/topology/sof/pipe-eq-iir-capture.m4 b/tools/topology/sof/pipe-eq-iir-capture.m4
@@ -47,7 +47,8 @@ C_CONTROLBYTES(DEF_EQIIR_COEF, PIPELINE_ID,
 W_PCM_CAPTURE(PCM_ID, EQ IIR Capture, 0, 2, SCHEDULE_CORE)
 
 # "EQ 0" has 2 sink period and x source periods
-W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, LIST(`		', "DEF_EQIIR_COEF"))
+W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, SCHEDULE_CORE,
+	LIST(`		', "DEF_EQIIR_COEF"))
 
 # Capture Buffers
 W_BUFFER(0, COMP_BUFFER_SIZE(2,

diff --git a/tools/topology/sof/pipe-eq-iir-eq-fir-volume-playback.m4 b/tools/topology/sof/pipe-eq-iir-eq-fir-volume-playback.m4
@@ -95,7 +95,8 @@ W_PGA(0, PIPELINE_FORMAT, DAI_PERIODS, 2, DEF_PGA_CONF, SCHEDULE_CORE,
 	LIST(`		', "PIPELINE_ID Master Playback Volume"))
 
 # "EQ 0" has 2 sink period and 2 source periods
-W_EQ_IIR(0, PIPELINE_FORMAT, 2, 2, LIST(`		', "DEF_EQIIR_COEF"))
+W_EQ_IIR(0, PIPELINE_FORMAT, 2, 2, SCHEDULE_CORE,
+	LIST(`		', "DEF_EQIIR_COEF"))
 
 # "EQ 0" has 2 sink period and 2 source periods
 W_EQ_FIR(0, PIPELINE_FORMAT, 2, 2, LIST(`		', "DEF_EQFIR_COEF"))

diff --git a/tools/topology/sof/pipe-eq-iir-playback.m4 b/tools/topology/sof/pipe-eq-iir-playback.m4
@@ -45,7 +45,8 @@ C_CONTROLBYTES(MY_CONTROLBYTES, PIPELINE_ID,
 W_PCM_PLAYBACK(PCM_ID, EQ IIR Playback, 2, 0, SCHEDULE_CORE)
 
 # "EQ 0" has x sink period and 2 source periods
-W_EQ_IIR(0, PIPELINE_FORMAT, DAI_PERIODS, 2, LIST(`		', "MY_CONTROLBYTES"))
+W_EQ_IIR(0, PIPELINE_FORMAT, DAI_PERIODS, 2, SCHEDULE_CORE,
+	LIST(`		', "MY_CONTROLBYTES"))
 
 # Playback Buffers
 W_BUFFER(0, COMP_BUFFER_SIZE(2,

diff --git a/tools/topology/sof/pipe-eq-iir-volume-capture-16khz.m4 b/tools/topology/sof/pipe-eq-iir-volume-capture-16khz.m4
@@ -76,7 +76,8 @@ W_PGA(0, PIPELINE_FORMAT, 2, 2, DEF_PGA_CONF, SCHEDULE_CORE,
 	LIST(`		', "CONTROL_NAME"))
 
 # "EQ 0" has 2 sink period and x source periods
-W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, LIST(`		', "DEF_EQIIR_COEF"))
+W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, SCHEDULE_CORE,
+	LIST(`		', "DEF_EQIIR_COEF"))
 
 # Capture Buffers
 W_BUFFER(0, COMP_BUFFER_SIZE(2,

diff --git a/tools/topology/sof/pipe-eq-iir-volume-capture.m4 b/tools/topology/sof/pipe-eq-iir-volume-capture.m4
@@ -93,7 +93,8 @@ W_PGA(0, PIPELINE_FORMAT, 2, 2, DEF_PGA_CONF, SCHEDULE_CORE,
 	"PIPELINE_ID CONTROL_NAME_SWITCH"))
 
 # "EQ 0" has 2 sink period and x source periods
-W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, LIST(`		', "DEF_EQIIR_COEF"))
+W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, SCHEDULE_CORE,
+	LIST(`		', "DEF_EQIIR_COEF"))
 
 # Capture Buffers
 W_BUFFER(0, COMP_BUFFER_SIZE(2,

diff --git a/tools/topology/sof/pipe-eq-iir-volume-playback.m4 b/tools/topology/sof/pipe-eq-iir-volume-playback.m4
@@ -72,7 +72,8 @@ W_PGA(0, PIPELINE_FORMAT, DAI_PERIODS, 2, DEF_PGA_CONF, SCHEDULE_CORE,
 	LIST(`		', "PIPELINE_ID Master Playback Volume"))
 
 # "EQ 0" has 2 sink period and 2 source periods
-W_EQ_IIR(0, PIPELINE_FORMAT, 2, 2, LIST(`		', "DEF_EQIIR_COEF"))
+W_EQ_IIR(0, PIPELINE_FORMAT, 2, 2, SCHEDULE_CORE,
+	LIST(`		', "DEF_EQIIR_COEF"))
 
 # Playback Buffers
 W_BUFFER(0, COMP_BUFFER_SIZE(2,

diff --git a/tools/topology/sof/pipe-highpass-capture.m4 b/tools/topology/sof/pipe-highpass-capture.m4
@@ -79,7 +79,7 @@ W_PGA(0, PIPELINE_FORMAT, 2, DAI_PERIODS, DEF_PGA_CONF, SCHEDULE_CORE,
 	LIST(`		', "PIPELINE_ID Master Capture Volume"))
 
 # "EQ_IIR 0" has 2 sink and x source periods
-W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS,
+W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, SCHEDULE_CORE,
 	LIST(`		', "DEF_EQIIR_COEF"))
 
 # Capture Buffers

diff --git a/tools/topology/sof/pipe-highpass-switch-capture.m4 b/tools/topology/sof/pipe-highpass-switch-capture.m4
@@ -89,7 +89,7 @@ W_PGA(0, PIPELINE_FORMAT, 2, DAI_PERIODS, DEF_PGA_CONF, SCHEDULE_CORE,
 	"PIPELINE_ID Master Capture Switch"))
 
 # "EQ_IIR 0" has 2 sink and x source periods
-W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS,
+W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, SCHEDULE_CORE,
 	LIST(`		', "DEF_EQIIR_COEF"))
 
 # Capture Buffers