kconfig: Add cores and memory sizes configurability

Signed-off-by: Jakub Dabek <jakub.dabek@linux.intel.com>
iganakov · Apr 18, 2019 · 7630647 · 7630647
1 parent 5d554c5
commit 7630647
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Showing 21 changed files with 114 additions and 58 deletions.
diff --git a/Kconfig b/Kconfig
@@ -2,6 +2,28 @@ mainmenu "SOF $(PROJECTVERSION) Configuration"
 
 comment "Compiler: $(CC_VERSION_TEXT)"
 
+menu "CAVS"
+
+config HP_MEMORY_BANKS
+	int "HP memory banks count"
+	depends on CAVS
+	default 8
+	help
+	  Available memory banks count for High Performance memory
+	  Lowering available banks could result in lower power consumption
+	  Too low count should result in unresponsive/crashing image due to not
+	  enough space for FW base image
+	  Banks are 64kb in size.
+
+config LP_MEMORY_BANKS
+	int "LP memory banks count"
+	default 1
+	depends on CAVS
+	help
+	  Available memory banks count for Low Power memory
+
+endmenu
+
 config HOST_PTABLE
 	bool
 	default n

diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
@@ -1,3 +1,4 @@
+add_subdirectory(platform)
 add_subdirectory(arch)
 
 if(BUILD_HOST)
@@ -17,5 +18,4 @@ add_subdirectory(init)
 add_subdirectory(ipc)
 add_subdirectory(lib)
 add_subdirectory(math)
-add_subdirectory(platform)
 add_subdirectory(tasks)
diff --git a/src/arch/xtensa/Kconfig b/src/arch/xtensa/Kconfig
@@ -8,4 +8,10 @@ config SMP
 	help
 	  Build SMP instead of UP
 
+config CORE_COUNT
+	int "Number of cores"
+	default 1
+	help
+	  Number of used cores
+	  Lowering available core count could result in lower power consumption
 endmenu
diff --git a/src/arch/xtensa/configs/apollolake_defconfig b/src/arch/xtensa/configs/apollolake_defconfig
@@ -1,3 +1,6 @@
 CONFIG_APOLLOLAKE=y
 CONFIG_CAVS_DMIC=y
 CONFIG_CAVS_SSP=y
+CONFIG_CORE_COUNT=2
+CONFIG_LP_MEMORY_BANKS=2
+CONFIG_HP_MEMORY_BANKS=8
diff --git a/src/arch/xtensa/configs/cannonlake_defconfig b/src/arch/xtensa/configs/cannonlake_defconfig
@@ -2,3 +2,6 @@ CONFIG_SMP=y
 CONFIG_CANNONLAKE=y
 CONFIG_CAVS_DMIC=y
 CONFIG_CAVS_SSP=y
+CONFIG_CORE_COUNT=4
+CONFIG_LP_MEMORY_BANKS=1
+CONFIG_HP_MEMORY_BANKS=47
diff --git a/src/arch/xtensa/configs/icelake_defconfig b/src/arch/xtensa/configs/icelake_defconfig
@@ -2,3 +2,6 @@ CONFIG_SMP=y
 CONFIG_ICELAKE=y
 CONFIG_CAVS_DMIC=y
 CONFIG_CAVS_SSP=y
+CONFIG_CORE_COUNT=4
+CONFIG_LP_MEMORY_BANKS=1
+CONFIG_HP_MEMORY_BANKS=47
diff --git a/src/arch/xtensa/configs/kabylake_defconfig b/src/arch/xtensa/configs/kabylake_defconfig
@@ -3,3 +3,6 @@ CONFIG_APOLLOLAKE=y
 CONFIG_FIRMWARE_SHORT_NAME="kbl"
 CONFIG_CAVS_DMIC=y
 CONFIG_CAVS_SSP=y
+CONFIG_CORE_COUNT=2
+CONFIG_LP_MEMORY_BANKS=2
+CONFIG_HP_MEMORY_BANKS=30
diff --git a/src/arch/xtensa/configs/skylake_defconfig b/src/arch/xtensa/configs/skylake_defconfig
@@ -3,3 +3,6 @@ CONFIG_APOLLOLAKE=y
 CONFIG_FIRMWARE_SHORT_NAME="skl"
 CONFIG_CAVS_DMIC=y
 CONFIG_CAVS_SSP=y
+CONFIG_CORE_COUNT=2
+CONFIG_LP_MEMORY_BANKS=2
+CONFIG_HP_MEMORY_BANKS=30
diff --git a/src/arch/xtensa/configs/suecreek_defconfig b/src/arch/xtensa/configs/suecreek_defconfig
@@ -1,3 +1,5 @@
 CONFIG_SUECREEK=y
 CONFIG_CAVS_DMIC=y
 CONFIG_CAVS_SSP=y
+CONFIG_CORE_COUNT=4
+CONFIG_LP_MEMORY_BANKS=1
diff --git a/src/drivers/intel/cavs/interrupt.c b/src/drivers/intel/cavs/interrupt.c
@@ -124,27 +124,28 @@ static void irq_lvl2_level5_handler(void *data)
 
 /* DSP internal interrupts */
 static struct irq_desc dsp_irq[PLATFORM_CORE_COUNT][4] = {
-#if CAVS_VERSION >= CAVS_VERSION_1_8
 	{{IRQ_NUM_EXT_LEVEL2, irq_lvl2_level2_handler, },
 	{IRQ_NUM_EXT_LEVEL3, irq_lvl2_level3_handler, },
 	{IRQ_NUM_EXT_LEVEL4, irq_lvl2_level4_handler, },
 	{IRQ_NUM_EXT_LEVEL5, irq_lvl2_level5_handler, } },
-
+#if PLATFORM_CORE_COUNT > 1
 	{{IRQ_NUM_EXT_LEVEL2, irq_lvl2_level2_handler, },
 	{IRQ_NUM_EXT_LEVEL3, irq_lvl2_level3_handler, },
 	{IRQ_NUM_EXT_LEVEL4, irq_lvl2_level4_handler, },
 	{IRQ_NUM_EXT_LEVEL5, irq_lvl2_level5_handler, } },
 #endif
-
+#if PLATFORM_CORE_COUNT > 2
 	{{IRQ_NUM_EXT_LEVEL2, irq_lvl2_level2_handler, },
 	{IRQ_NUM_EXT_LEVEL3, irq_lvl2_level3_handler, },
 	{IRQ_NUM_EXT_LEVEL4, irq_lvl2_level4_handler, },
 	{IRQ_NUM_EXT_LEVEL5, irq_lvl2_level5_handler, } },
-
+#endif
+#if PLATFORM_CORE_COUNT > 3
 	{{IRQ_NUM_EXT_LEVEL2, irq_lvl2_level2_handler, },
 	{IRQ_NUM_EXT_LEVEL3, irq_lvl2_level3_handler, },
 	{IRQ_NUM_EXT_LEVEL4, irq_lvl2_level4_handler, },
 	{IRQ_NUM_EXT_LEVEL5, irq_lvl2_level5_handler, } },
+#endif
 };
 
 struct irq_desc *platform_irq_get_parent(uint32_t irq)

diff --git a/src/platform/Kconfig b/src/platform/Kconfig
@@ -104,7 +104,7 @@ config ICELAKE
 	select CAVS
 	select CAVS_VERSION_2_0
 	help
-	  Select if your target platform is Icelake-compatible
+		Select if your target platform is Icelake-compatible
 
 endchoice
 

diff --git a/src/platform/apollolake/include/platform/asm_memory_management.h b/src/platform/apollolake/include/platform/asm_memory_management.h
@@ -53,7 +53,7 @@
 	// SEGMENT #0
 	movi \az, (SHIM_BASE + SHIM_HSPGISTS)
 	movi \ax, (SHIM_BASE + SHIM_HSPGCTL)
-	movi \ay, HPSRAM_MASK()
+	movi \ay, HPSRAM_MASK(0)
 	s32i \ay, \ax, 0
 	memw
 	/* since HPSRAM EBB bank #0 might be used as buffer for legacy

diff --git a/src/platform/apollolake/include/platform/memory.h b/src/platform/apollolake/include/platform/memory.h
@@ -35,10 +35,8 @@
 
 #include <config.h>
 #include <arch/memory.h>
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
 #include <cavs/memory.h>
-#endif
+
 /* physical DSP addresses */
 
 /* shim */
@@ -330,6 +328,8 @@
 #define SOF_STACK_BASE		(HP_SRAM_BASE + HP_SRAM_SIZE)
 #define SOF_STACK_END		(SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE)
 
+#define SOF_MEMORY_SIZE		(SOF_STACK_BASE - HP_SRAM_BASE)
+
 /*
  * The LP SRAM Heap and Stack on Apollolake are organised like this :-
  *

diff --git a/src/platform/apollolake/include/platform/platform.h b/src/platform/apollolake/include/platform/platform.h
@@ -33,24 +33,19 @@
 #ifndef __PLATFORM_PLATFORM_H__
 #define __PLATFORM_PLATFORM_H__
 
+#include <cavs/memory.h>
+
 #define PLATFORM_RESET_MHE_AT_BOOT		1
 
 #define PLATFORM_DISABLE_L2CACHE_AT_BOOT	1
 
-#define PLATFORM_CORE_COUNT			2
-
-#define PLATFORM_LPSRAM_EBB_COUNT		2
-
-#define PLATFORM_HPSRAM_EBB_COUNT		8
-
-#define PLATFORM_HPSRAM_SEGMENTS		1
-
 #define PLATFORM_MASTER_CORE_ID			0
 
-#define HPSRAM_MASK(ignored)	((1 << PLATFORM_HPSRAM_EBB_COUNT) - 1)
-#define LPSRAM_MASK(ignored)	((1 << PLATFORM_LPSRAM_EBB_COUNT) - 1)
-#define LPSRAM_BANK_SIZE (64 * 1024)
-#define LPSRAM_SIZE (PLATFORM_LPSRAM_EBB_COUNT * LPSRAM_BANK_SIZE)
+#define MAX_CORE_COUNT				2
+
+#if PLATFORM_CORE_COUNT > MAX_CORE_COUNT
+#error "Invalid core count - exceeding core limit"
+#endif
 
 #if !defined(__ASSEMBLER__) && !defined(LINKER)
 

diff --git a/src/platform/cannonlake/include/platform/asm_memory_management.h b/src/platform/cannonlake/include/platform/asm_memory_management.h
@@ -87,7 +87,7 @@
 .macro m_cavs_lpsram_power_down_entire ax, ay, az
 	movi \az, LSPGISTS
 	movi \ax, LSPGCTL
-	movi \ay, LPSRAM_MASK
+	movi \ay, LPSRAM_MASK()
 	s32i \ay, \ax, 0
 	memw
   // assumed that HDA shared dma buffer will be in LPSRAM

diff --git a/src/platform/cannonlake/include/platform/memory.h b/src/platform/cannonlake/include/platform/memory.h
@@ -35,10 +35,7 @@
 
 #include <config.h>
 #include <arch/memory.h>
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
 #include <cavs/memory.h>
-#endif
 
 /* physical DSP addresses */
 

diff --git a/src/platform/cannonlake/include/platform/platform.h b/src/platform/cannonlake/include/platform/platform.h
@@ -34,34 +34,19 @@
 #ifndef __PLATFORM_PLATFORM_H__
 #define __PLATFORM_PLATFORM_H__
 
+#include <cavs/memory.h>
+
 #define PLATFORM_RESET_MHE_AT_BOOT	1
 
 #define PLATFORM_MEM_INIT_AT_BOOT	1
 
-#define PLATFORM_CORE_COUNT		4
-
-#define PLATFORM_LPSRAM_EBB_COUNT	1
-
-#define PLATFORM_HPSRAM_EBB_COUNT	47
-
-#define PLATFORM_HPSRAM_SEGMENTS	2
-
 #define PLATFORM_MASTER_CORE_ID		0
 
-//TODO: move cAVS memory specific definitions to cavs/memory driver
-#define SRAM_BANK_SIZE			0x10000
-
-#define EBB_SEGMENT_SIZE		32
+#define MAX_CORE_COUNT			4
 
-#define MAX_EBB_BANKS_IN_SEGMENT	32
-#define HPSRAM_MASK(seg_idx)\
-	((1 << (PLATFORM_HPSRAM_EBB_COUNT\
-	 - MAX_EBB_BANKS_IN_SEGMENT * seg_idx)) - 1)
-#define LPSRAM_MASK	((1 << PLATFORM_LPSRAM_EBB_COUNT) - 1)
-#define MAX_MEMORY_SEGMENTS ((PLATFORM_HPSRAM_EBB_COUNT + \
-	MAX_EBB_BANKS_IN_SEGMENT - 1) / MAX_EBB_BANKS_IN_SEGMENT)
-#define LPSRAM_BANK_SIZE (64 * 1024)
-#define LPSRAM_SIZE (PLATFORM_LPSRAM_EBB_COUNT * LPSRAM_BANK_SIZE)
+#if PLATFORM_CORE_COUNT > MAX_CORE_COUNT
+#error "Invalid core count - exceeding core limit"
+#endif
 
 #if !defined(__ASSEMBLER__) && !defined(LINKER)
 

diff --git a/src/platform/icelake/include/platform/memory.h b/src/platform/icelake/include/platform/memory.h
@@ -307,6 +307,8 @@
 #define HEAP_BUFFER_BLOCK_SIZE		0x180
 #define HEAP_BUFFER_COUNT	(HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
 
+#define SOF_MEMORY_SIZE		(SOF_STACK_BASE - HP_SRAM_BASE)
+
 /*
  * The LP SRAM Heap and Stack on Icelake are organised like this :-
  *

diff --git a/src/platform/icelake/include/platform/platform.h b/src/platform/icelake/include/platform/platform.h
@@ -34,19 +34,19 @@
 #ifndef __PLATFORM_PLATFORM_H__
 #define __PLATFORM_PLATFORM_H__
 
+#include <cavs/memory.h>
+
 #define PLATFORM_RESET_MHE_AT_BOOT	1
 
 #define PLATFORM_MEM_INIT_AT_BOOT	1
 
-#define PLATFORM_CORE_COUNT		4
-
 #define PLATFORM_MASTER_CORE_ID		0
 
-#define PLATFORM_LPSRAM_EBB_COUNT	1
+#define MAX_CORE_COUNT			4
 
-#define LPSRAM_BANK_SIZE (64 * 1024)
-
-#define LPSRAM_SIZE (PLATFORM_LPSRAM_EBB_COUNT * LPSRAM_BANK_SIZE)
+#if PLATFORM_CORE_COUNT > MAX_CORE_COUNT
+#error "Invalid core count - exceeding core limit"
+#endif
 
 #if !defined(__ASSEMBLER__) && !defined(LINKER)
 

diff --git a/src/platform/intel/cavs/include/cavs/memory.h b/src/platform/intel/cavs/include/cavs/memory.h
@@ -31,6 +31,36 @@
 #ifndef __INCLUDE_CAVS_MEM_MAP__
 #define __INCLUDE_CAVS_MEM_MAP__
 
+#include <config.h>
+
+#define LPSRAM_BANK_SIZE (64 * 1024)
+
+#define SRAM_BANK_SIZE			LPSRAM_BANK_SIZE
+
+#define EBB_BANKS_IN_SEGMENT		32
+
+#define EBB_SEGMENT_SIZE		EBB_BANKS_IN_SEGMENT
+
+#define PLATFORM_CORE_COUNT		CONFIG_CORE_COUNT
+
+#define PLATFORM_LPSRAM_EBB_COUNT	CONFIG_LP_MEMORY_BANKS
+
+#define PLATFORM_HPSRAM_EBB_COUNT	CONFIG_HP_MEMORY_BANKS
+
+#define MAX_MEMORY_SEGMENTS		PLATFORM_HPSRAM_SEGMENTS
+
+#define PLATFORM_HPSRAM_SEGMENTS	((PLATFORM_HPSRAM_EBB_COUNT \
+	+ EBB_BANKS_IN_SEGMENT - 1) / EBB_BANKS_IN_SEGMENT)
+
+#define LPSRAM_MASK(ignored)	((1 << PLATFORM_LPSRAM_EBB_COUNT) - 1)
+
+#define HPSRAM_MASK(seg_idx)	((1 << (PLATFORM_HPSRAM_EBB_COUNT \
+	- EBB_BANKS_IN_SEGMENT * seg_idx)) - 1)
+
+#define LPSRAM_SIZE (PLATFORM_LPSRAM_EBB_COUNT * LPSRAM_BANK_SIZE)
+
+#if !defined(__ASSEMBLER__) && !defined(LINKER)
 void platform_init_memmap(void);
+#endif
 
 #endif
diff --git a/src/platform/suecreek/include/platform/platform.h b/src/platform/suecreek/include/platform/platform.h
@@ -34,18 +34,19 @@
 #ifndef __PLATFORM_PLATFORM_H__
 #define __PLATFORM_PLATFORM_H__
 
+#include <cavs/memory.h>
+
 #define PLATFORM_RESET_MHE_AT_BOOT	1
 
 #define PLATFORM_MEM_INIT_AT_BOOT	1
 
-#define PLATFORM_CORE_COUNT		4
-
 #define PLATFORM_MASTER_CORE_ID		0
-#define PLATFORM_LPSRAM_EBB_COUNT	1
 
-#define LPSRAM_BANK_SIZE (64 * 1024)
+#define MAX_CORE_COUNT			4
 
-#define LPSRAM_SIZE (PLATFORM_LPSRAM_EBB_COUNT * LPSRAM_BANK_SIZE)
+#if PLATFORM_CORE_COUNT > MAX_CORE_COUNT
+#error "Invalid core count - exceeding core limit"
+#endif
 
 #if !defined(__ASSEMBLER__) && !defined(LINKER)