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phase_rec_loop

Implementing Carrier Phase Recovery Loop Using Vivado HLS

This readme file contains these sections:

  1. OVERVIEW
  2. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS
  3. DESIGN FILE HIERARCHY
  4. INSTALLATION AND OPERATING INSTRUCTIONS
  5. OTHER INFORMATION (OPTIONAL)
  6. SUPPORT
  7. LICENSE
  8. CONTRIBUTING
  9. Acknowledgements
  10. REVISION HISTORY

1. OVERVIEW

This application note describes the implementation of a carrier phase recovery loop algorithm for a single carrier QAM demodulator using Vivado High-Level Synthesis (HLS). The algorithm, described in C/C++, is compiled to synthesizable RTL by Vivado HLS, added as a block to System Generator for DSP for verification, and then implemented using the Vivado Design Suite.

The automatic resource assignment, sharing, and scheduling capability of Vivado HLS is instrumental in compiling a complex algorithm into a solution optimized for both performance and resource usage.The proposed design methodology can be applied to expedite the implementation of other common baseband signal processing algorithms, such as timing recovery loops, MIMO decoders, and adaptive equalizers.

Full Documentation

2. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS

Any Vivado HLS release from 2014.1 to 2016.1

3. DESIGN FILE HIERARCHY

	cin.txt
    CONTRIBUTING.md
    cout.txt
    crec.cpp
    crec.h
    crec_tb.cpp
    lf_cin.txt
    lf_phin.txt
    LICENSE.md
    makefile.txt
    README.md
    run.tcl
    table.txt

4. INSTALLATION AND OPERATING INSTRUCTIONS

The procedure to build the HLS project is as follows:

TCL file to run HLS tool:

vivado_hls run.tcl

5. OTHER INFORMATION

For more information check here: Full Documentation Vivado HLS User Guide

6. SUPPORT

For questions and to get help on this project or your own projects, visit the Vivado HLS Forums.

7. License

The source for this project is licensed under the 3-Clause BSD License

8. Contributing code

Please refer to and read the Contributing document for guidelines on how to contribute code to this open source project. The code in the /master branch is considered to be stable, and all pull-requests should be made against the /develop branch.

9. Acknowledgements

The Library is written by developers at Xilinx with other contributors listed below:

10. REVISION HISTORY

Date Readme Version Revision Description
JAN2014 1.0 Initial Xilinx release
24MAR2016 1.1 Verified for 2016.1