This readme file contains these sections:
- OVERVIEW
- SOFTWARE TOOLS AND SYSTEM REQUIREMENTS
- DESIGN FILE HIERARCHY
- INSTALLATION AND OPERATING INSTRUCTIONS
- OTHER INFORMATION (OPTIONAL)
- SUPPORT
- LICENSE
- CONTRIBUTING
- Acknowledgements
- REVISION HISTORY
This application note describes the implementation of a carrier phase recovery loop algorithm for a single carrier QAM demodulator using Vivado High-Level Synthesis (HLS). The algorithm, described in C/C++, is compiled to synthesizable RTL by Vivado HLS, added as a block to System Generator for DSP for verification, and then implemented using the Vivado Design Suite.
The automatic resource assignment, sharing, and scheduling capability of Vivado HLS is instrumental in compiling a complex algorithm into a solution optimized for both performance and resource usage.The proposed design methodology can be applied to expedite the implementation of other common baseband signal processing algorithms, such as timing recovery loops, MIMO decoders, and adaptive equalizers.
Any Vivado HLS release from 2014.1 to 2016.1
cin.txt
CONTRIBUTING.md
cout.txt
crec.cpp
crec.h
crec_tb.cpp
lf_cin.txt
lf_phin.txt
LICENSE.md
makefile.txt
README.md
run.tcl
table.txt
The procedure to build the HLS project is as follows:
TCL file to run HLS tool:
vivado_hls run.tcl
For more information check here: Full Documentation Vivado HLS User Guide
For questions and to get help on this project or your own projects, visit the Vivado HLS Forums.
The source for this project is licensed under the 3-Clause BSD License
Please refer to and read the Contributing document for guidelines on how to contribute code to this open source project. The code in the /master
branch is considered to be stable, and all pull-requests should be made against the /develop
branch.
The Library is written by developers at Xilinx with other contributors listed below:
Date | Readme Version | Revision Description |
---|---|---|
JAN2014 | 1.0 | Initial Xilinx release |
24MAR2016 | 1.1 | Verified for 2016.1 |