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Add vector instructions to RISC-V emitter #16829

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merged 11 commits into from
Jan 22, 2023
Merged

Add vector instructions to RISC-V emitter #16829

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bfd60a6
riscv: Add vector load/store ops.
unknownbrackets Jan 21, 2023
6fa50ea
riscv: Add vector int add/sub and many encodings.
unknownbrackets Jan 22, 2023
b3be901
riscv: Add vector bitwise/compare funcs.
unknownbrackets Jan 22, 2023
6f78f2a
riscv: Add vector integer muliplies.
unknownbrackets Jan 22, 2023
a313e44
riscv: Add vector integer move/broadcast.
unknownbrackets Jan 22, 2023
a1ca291
riscv: Add vector fixed-point arith instructions.
unknownbrackets Jan 22, 2023
f079667
riscv: Add vector float arith/mul funcs.
unknownbrackets Jan 22, 2023
2a7bdbf
riscv: Add vector float move/compare/unary.
unknownbrackets Jan 22, 2023
88de043
riscv: Add vector reduce instructions.
unknownbrackets Jan 22, 2023
c99eb18
riscv: Add vector mask instructions.
unknownbrackets Jan 22, 2023
2aeee83
riscv: Add vector transfer instructions.
unknownbrackets Jan 22, 2023
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riscv: Add vector reduce instructions.
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@unknownbrackets
unknownbrackets committed Jan 22, 2023
commit 88de043329ff6e780b7a94ed94a23f28c9cb6ac5
64 changes: 64 additions & 0 deletions Common/RiscVEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3270,6 +3270,70 @@ void RiscVEmitter::VFNCVT_ROD_F_F_V(RiscVReg vd, RiscVReg vs2, VUseMask vm) {
Write32(EncodeFVV(vd, (RiscVReg)Funct5::VFNCVT_ROD_F_F, vs2, vm, Funct6::VFXUNARY0));
}

void RiscVEmitter::VREDSUM_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VREDSUM));
}

void RiscVEmitter::VREDMAXU_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VMAXU));
}

void RiscVEmitter::VREDMAX_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VMAX));
}

void RiscVEmitter::VREDMINU_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VMINU));
}

void RiscVEmitter::VREDMIN_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VMIN));
}

void RiscVEmitter::VREDAND_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VREDAND));
}

void RiscVEmitter::VREDOR_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VREDOR));
}

void RiscVEmitter::VREDXOR_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VREDXOR));
}

void RiscVEmitter::VWREDSUMU_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeIVV(vd, vs1, vs2, vm, Funct6::VWREDSUMU));
}

void RiscVEmitter::VWREDSUM_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeIVV(vd, vs1, vs2, vm, Funct6::VWREDSUM));
}

void RiscVEmitter::VFREDOSUM_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeFVV(vd, vs1, vs2, vm, Funct6::VFREDOSUM));
}

void RiscVEmitter::VFREDUSUM_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeFVV(vd, vs1, vs2, vm, Funct6::VFREDUSUM));
}

void RiscVEmitter::VFREDMAX_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeFVV(vd, vs1, vs2, vm, Funct6::VMAX));
}

void RiscVEmitter::VFREDMIN_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeFVV(vd, vs1, vs2, vm, Funct6::VMIN));
}

void RiscVEmitter::VFWREDOSUM_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeFVV(vd, vs1, vs2, vm, Funct6::VFWREDOSUM));
}

void RiscVEmitter::VFWREDUSUM_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeFVV(vd, vs1, vs2, vm, Funct6::VFWREDUSUM));
}

bool RiscVEmitter::AutoCompress() const {
return SupportsCompressed() && autoCompress_;
}
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18 changes: 18 additions & 0 deletions Common/RiscVEmitter.h
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Original file line number Diff line number Diff line change
Expand Up @@ -798,6 +798,24 @@ class RiscVEmitter {
void VFNCVT_F_F_V(RiscVReg vd, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
void VFNCVT_ROD_F_F_V(RiscVReg vd, RiscVReg vs2, VUseMask vm = VUseMask::NONE);

void VREDSUM_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VREDMAXU_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VREDMAX_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VREDMINU_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VREDMIN_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VREDAND_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VREDOR_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VREDXOR_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VWREDSUMU_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VWREDSUM_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);

void VFREDOSUM_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VFREDUSUM_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VFREDMAX_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VFREDMIN_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VFWREDOSUM_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VFWREDUSUM_VS(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);

// Compressed instructions.
void C_ADDI4SPN(RiscVReg rd, u32 nzuimm10);
void C_FLD(RiscVReg rd, RiscVReg addr, u8 uimm8);
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