diff --git a/Core/CoreTiming.cpp b/Core/CoreTiming.cpp
index da24649553ca..c75db0a08fc2 100644
--- a/Core/CoreTiming.cpp
+++ b/Core/CoreTiming.cpp
@@ -585,6 +585,8 @@ void ForceCheck()
 	int cyclesExecuted = slicelength - currentMIPS->downcount;
 	globalTimer += cyclesExecuted;
 	// This will cause us to check for new events immediately.
+	// NOTE: This causes problems on ARM32 in certain contexts due to jo.downcountInRegister.
+	// Not 100% sure what's going on there yet.
 	currentMIPS->downcount = -1;
 	// But let's not eat a bunch more time in Advance() because of this.
 	slicelength = -1;
diff --git a/Core/MIPS/JitCommon/JitState.cpp b/Core/MIPS/JitCommon/JitState.cpp
index 032651924534..6da26656c29c 100644
--- a/Core/MIPS/JitCommon/JitState.cpp
+++ b/Core/MIPS/JitCommon/JitState.cpp
@@ -37,7 +37,7 @@ namespace MIPSComp {
 
 		// ARM only
 		downcountInRegister = true;
-		useNEONVFPU = false;  // true
+		useNEONVFPU = false;
 		if (Disabled(JitDisable::SIMD))
 			useNEONVFPU = false;
 
diff --git a/Core/MIPS/MIPS.cpp b/Core/MIPS/MIPS.cpp
index 5aeeacbbf88d..b31dfe63e2ff 100644
--- a/Core/MIPS/MIPS.cpp
+++ b/Core/MIPS/MIPS.cpp
@@ -370,7 +370,9 @@ void MIPSState::InvalidateICache(u32 address, int length) {
 		if (coreState == CORE_RUNNING || insideJit) {
 			pendingClears.emplace_back(address, length);
 			hasPendingClears = true;
+#if !PPSSPP_ARCH(ARM) // See comment in ForceCheck
 			CoreTiming::ForceCheck();
+#endif
 		} else {
 			MIPSComp::jit->InvalidateCacheAt(address, length);
 		}
@@ -383,7 +385,9 @@ void MIPSState::ClearJitCache() {
 		if (coreState == CORE_RUNNING || insideJit) {
 			pendingClears.emplace_back(0, 0);
 			hasPendingClears = true;
+#if !PPSSPP_ARCH(ARM) // See comment in ForceCheck
 			CoreTiming::ForceCheck();
+#endif
 		} else {
 			MIPSComp::jit->ClearCache();
 		}