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👋 Hi there
I love everything about computer architecture. Follow me to see my project evolutions.
A completely configurable RISC-V Out of Order Core with a base model geared towards maximizing performance
SystemVerilog 8 2
C
Litex/Migen project repository
Python 2 1
Fast Multiplication algorithm in SystemVerilog by using 4 to 2 compressors
SystemVerilog 1