Popular repositories Loading

1. find_first_set find_first_set Public

   Verilog RTL to find the first bit set in a vector.

   SystemVerilog 2

2. async_fifo async_fifo Public

   Asynchronous FIFO using flop-based memory with one cycle read latency.

   SystemVerilog 1

3. toggle_sync toggle_sync Public

   Implements simple data handshake between two clock domains

   SystemVerilog 1

4. double-buffered-reorder-fifo double-buffered-reorder-fifo Public

   A parameterized number of data words are written into a reorder memory and then popped out in order when memory is full.

   SystemVerilog 1 1

5. classifier classifier Public

   A module to do lookup and classification using cuckoo hashing.

   SystemVerilog 1 1

6. sync_fifo_0 sync_fifo_0 Public

   Synchronous FIFO interfacing with flop-based, zero-delay read latency memory.

   SystemVerilog