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Add generator for bin based plots for FETs #237

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Add generator for bin based plots for FETs #237

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3f11b65
Added initial script for generating plots from FET simulator
glatosinski Nov 10, 2020
508c21f
Added script for generating nfet and pfet plots from libraries directory
glatosinski Nov 11, 2020
5ea3ea9
Added grid to plots
glatosinski Nov 12, 2020
414b809
Added closing plots after saving to file
glatosinski Nov 12, 2020
3e57ce2
Comment out not working fet
glatosinski Nov 12, 2020
c64020c
FET simulator code cleanup
glatosinski Nov 12, 2020
2aed534
Added ngspice to environment.yml and PySpice to requirements.txt
glatosinski Nov 16, 2020
ee63e6c
Added grouping FET plots by W
glatosinski Nov 16, 2020
c8b18d8
Changed extension for FET plots from PNG to SVG
glatosinski Nov 16, 2020
f177fa7
Wrapped script in main function
glatosinski Nov 16, 2020
222572a
Added fetching FETs by regular expression
glatosinski Nov 17, 2020
7c4d2fa
Added proper closing of plots
glatosinski Nov 17, 2020
3f0a64b
Fixed directory generation
glatosinski Nov 18, 2020
1c0eeda
Added releasing memory after plotting the FET graphs
glatosinski Nov 18, 2020
6709fdf
Added not failing on invalid bins.csv file
glatosinski Nov 18, 2020
7f0f405
Added notification on successful finish of the script
glatosinski Nov 18, 2020
8d734f0
fet_simulator: added docstrings
glatosinski Nov 24, 2020
d760ac4
fet_simulator: moved fet modules to simulation/analog
glatosinski Nov 25, 2020
77bad0d
fet_simulator: used more elaborate variable names
glatosinski Nov 25, 2020
ee006e4
base: added method for parsing bins.csv files
glatosinski Nov 25, 2020
a4f7529
fet: added using bins.csv parser from skywater_pdk.base
glatosinski Nov 25, 2020
a512ddf
fet: added docstrings for modules
glatosinski Nov 25, 2020
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FET simulator code cleanup 
Signed-off-by: Grzegorz Latosinski <glatosinski@antmicro.com>
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@glatosinski
glatosinski committed Nov 25, 2020
commit c64020cb8bd4855207cc0fe1166981cfc2fcdd96
35 changes: 21 additions & 14 deletions scripts/python-skywater-pdk/skywater_pdk/fet_simulator/fet_simulator.py
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Original file line number Diff line number Diff line change
Expand Up @@ -18,42 +18,48 @@
# SPDX-License-Identifier: Apache-2.0

import PySpice.Logging.Logging as Logging
logger = Logging.setup_logging()
from PySpice.Spice.Netlist import Circuit
from PySpice.Unit import *
from PySpice.Unit import u_V
import matplotlib.pyplot as plt
from pathlib import Path
import csv

logger = Logging.setup_logging()


def create_test_circuit(fet_type, iparam, fet_L, fet_W, corner_path):
c=Circuit('gm_id')
c = Circuit('gm_id')
c.include(corner_path)

# create the circuit
c.V('gg', 1, c.gnd, 0@u_V)
c.V('dd', 2, c.gnd, 1.8@u_V)
c.X('M1', fet_type, 2, 1, c.gnd, c.gnd, L=fet_L, W=fet_W, ad="'W*0.29'",
pd="'2*(W+0.29)'", as_="'W*0.29'", ps="'2*(W+0.29)'", nrd="'0.29/W'",
c.X(
'M1', fet_type, 2, 1, c.gnd, c.gnd, L=fet_L, W=fet_W, ad="'W*0.29'",
pd="'2*(W+0.29)'", as_="'W*0.29'", ps="'2*(W+0.29)'", nrd="'0.29/W'",
nrs="'0.29/W'", sa=0, sb=0, sd=0, nf=1, mult=1
)
return c
return c


def run_sim(c, iparam, fet_W):
sim = c.simulator()
sim.save_internal_parameters(
iparam%'gm', iparam%'id', iparam%'gds', iparam%'cgg'
iparam % 'gm', iparam % 'id', iparam % 'gds', iparam % 'cgg'
)

# run the dc simulation
an = sim.dc(Vgg=slice(0, 1.8, 0.01))

# calculate needed values..need as_ndarray() since most of these have None as the unit and that causes an error
gm_id = an.internal_parameters[iparam%'gm'].as_ndarray() / an.internal_parameters[iparam%'id'].as_ndarray()
ft = an.internal_parameters[iparam%'gm'].as_ndarray() / an.internal_parameters[iparam%'cgg'].as_ndarray()
id_W = an.internal_parameters[iparam%'id'].as_ndarray() / fet_W
gm_gds = an.internal_parameters[iparam%'gm'].as_ndarray() / an.internal_parameters[iparam%'gds'].as_ndarray()
# calculate needed values..need as_ndarray() since most of these have None
# as the unit and that causes an error
gm_id = (an.internal_parameters[iparam % 'gm'].as_ndarray() /
an.internal_parameters[iparam % 'id'].as_ndarray())
ft = (an.internal_parameters[iparam % 'gm'].as_ndarray() /
an.internal_parameters[iparam % 'cgg'].as_ndarray())
id_W = (an.internal_parameters[iparam % 'id'].as_ndarray() / fet_W)
gm_gds = (an.internal_parameters[iparam % 'gm'].as_ndarray() /
an.internal_parameters[iparam % 'gds'].as_ndarray())

return gm_id, ft, id_W, gm_gds, an.nodes['v-sweep']

Expand Down Expand Up @@ -101,8 +107,9 @@ def generate_fet_plots(
outdir,
outprefix,
only_W=None,
ext='png'):
print(f'[generate_fet_plots] {fet_type} {corner_path} {bins_csv} {outdir} {outprefix} {only_W}')
ext='svg'):
print(f'[generate_fet_plots] {fet_type} {corner_path} {bins_csv}' +
f'{outdir} {outprefix} {only_W}')
iparam = f'@m.xm1.m{fet_type}[%s]'
# fet_W and fet_L values here are only for initialization, they are
# later changed in the for loop
Expand Down
6 changes: 3 additions & 3 deletions scripts/python-skywater-pdk/skywater_pdk/fet_simulator/generate-docs-plots.py
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Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@
['nfet_03v3_nvt-and-nfet_05v0_nvt', 'nfet_03v3_nvt', None],
['nfet_05v0_nvt', 'nfet_05v0_nvt', None],
# ['nfet_20v0'], TODO provide
# ['nfet_20v0_iso', 'nfet_20v0_nvt_iso', None], TODO invalid bins.csv file
# ['nfet_20v0_iso', 'nfet_20v0_nvt_iso', None], TODO invalid bins.csv
# ['nfet_20v0_nvt', 'nfet_20v0_nvt', None], TODO invalid bins.csv file
# ['nfet_20v0_zvt', 'nfet_20v0_zvt', None], TODO invalid bins.csv file
# ['nfet_g11v0d16v0'], TODO provide
Expand All @@ -65,8 +65,8 @@
generate_fet_plots(
f'sky130_fd_pr__{fetname}',
typicalcorner,
args.fd_pr_dir / f'cells/{fetname}/sky130_fd_pr__{fetname}.bins.csv',
args.device_details_dir / outdir,
args.fd_pr_dir/f'cells/{fetname}/sky130_fd_pr__{fetname}.bins.csv',
args.device_details_dir/outdir,
f'sim_{fetname}_',
onlyw
)