fixed data pack in rocev2

fpgasystems · Aug 24, 2019 · 0cc7427 · 0cc7427
1 parent 7896826
commit 0cc7427
Showing 1 changed file with 29 additions and 22 deletions.
diff --git a/hdl/common/roce_stack.sv b/hdl/common/roce_stack.sv
@@ -3,7 +3,7 @@
 
 `include "os_types.svh"
 
-`define POINTER_CHASING
+//`define POINTER_CHASING
 
 module roce_stack #(
     parameter ROCE_EN = 1
@@ -49,8 +49,8 @@ module roce_stack #(
 generate
 if (ROCE_EN == 1) begin
 rocev2_ip rocev2_inst(
-    .aclk(net_clk), // input aclk
-    .aresetn(net_aresetn), // input aresetn
+    .ap_clk(net_clk), // input aclk
+    .ap_rst_n(net_aresetn), // input aresetn
     //RX
 //`ifdef IP_VERSION4
      //IPv4
@@ -74,9 +74,9 @@ rocev2_ip rocev2_inst(
     .m_axis_rx_data_TKEEP(),
     .m_axis_rx_data_TLAST(),*/
     //TX
-    .s_axis_tx_meta_TVALID(s_axis_tx_meta.valid),
-    .s_axis_tx_meta_TREADY(s_axis_tx_meta.ready),
-    .s_axis_tx_meta_TDATA(s_axis_tx_meta.data),
+    .s_axis_tx_meta_V_TVALID(s_axis_tx_meta.valid),
+    .s_axis_tx_meta_V_TREADY(s_axis_tx_meta.ready),
+    .s_axis_tx_meta_V_TDATA(s_axis_tx_meta.data),
     .s_axis_tx_data_TVALID(s_axis_tx_data.valid),
     .s_axis_tx_data_TREADY(s_axis_tx_data.ready),
     .s_axis_tx_data_TDATA(s_axis_tx_data.data),
@@ -93,11 +93,13 @@ rocev2_ip rocev2_inst(
     //Memory
     .m_axis_mem_write_cmd_TVALID(m_axis_mem_write_cmd.valid),
     .m_axis_mem_write_cmd_TREADY(m_axis_mem_write_cmd.ready),
-    .m_axis_mem_write_cmd_TDATA({m_axis_mem_write_cmd.dest, m_axis_mem_write_cmd.data}),
+    .m_axis_mem_write_cmd_TDATA(m_axis_mem_write_cmd.data),
+    .m_axis_mem_write_cmd_TDEST(m_axis_mem_write_cmd.dest),
 
     .m_axis_mem_read_cmd_TVALID(m_axis_mem_read_cmd.valid),
     .m_axis_mem_read_cmd_TREADY(m_axis_mem_read_cmd.ready),
-    .m_axis_mem_read_cmd_TDATA({m_axis_mem_read_cmd.dest, m_axis_mem_read_cmd.data}),
+    .m_axis_mem_read_cmd_TDATA(m_axis_mem_read_cmd.data),
+    .m_axis_mem_read_cmd_TDEST(m_axis_mem_read_cmd.dest),
     // Memory Write
     .m_axis_mem_write_data_TVALID(m_axis_mem_write_data.valid),
     .m_axis_mem_write_data_TREADY(m_axis_mem_write_data.ready),
@@ -117,21 +119,21 @@ rocev2_ip rocev2_inst(
     //.s_axis_mem_write_status_TDATA(s_axis_rxwrite_sts_TDATA),
 
     //Pointer chaising
-`ifdef POINTER_CHASING
-    .m_axis_rx_pcmeta_TVALID(m_axis_rx_pcmeta.valid),
-    .m_axis_rx_pcmeta_TREADY(m_axis_rx_pcmeta.ready),
-    .m_axis_rx_pcmeta_TDATA(m_axis_rx_pcmeta.data),
-    .s_axis_tx_pcmeta_TVALID(s_axis_tx_pcmeta.valid),
-    .s_axis_tx_pcmeta_TREADY(s_axis_tx_pcmeta.ready),
-    .s_axis_tx_pcmeta_TDATA(s_axis_tx_pcmeta.data),
-`endif
+/*`ifdef POINTER_CHASING
+    .m_axis_rx_pcmeta_V_TVALID(m_axis_rx_pcmeta.valid),
+    .m_axis_rx_pcmeta_V_TREADY(m_axis_rx_pcmeta.ready),
+    .m_axis_rx_pcmeta_V_TDATA(m_axis_rx_pcmeta.data),
+    .s_axis_tx_pcmeta_V_TVALID(s_axis_tx_pcmeta.valid),
+    .s_axis_tx_pcmeta_V_TREADY(s_axis_tx_pcmeta.ready),
+    .s_axis_tx_pcmeta_V_TDATA(s_axis_tx_pcmeta.data),
+`endif*/
     //CONTROL
-    .s_axis_qp_interface_TVALID(s_axis_qp_interface.valid),
-    .s_axis_qp_interface_TREADY(s_axis_qp_interface.ready),
-    .s_axis_qp_interface_TDATA(s_axis_qp_interface.data),
-    .s_axis_qp_conn_interface_TVALID(s_axis_qp_conn_interface.valid),
-    .s_axis_qp_conn_interface_TREADY(s_axis_qp_conn_interface.ready),
-    .s_axis_qp_conn_interface_TDATA(s_axis_qp_conn_interface.data),
+    .s_axis_qp_interface_V_TVALID(s_axis_qp_interface.valid),
+    .s_axis_qp_interface_V_TREADY(s_axis_qp_interface.ready),
+    .s_axis_qp_interface_V_TDATA(s_axis_qp_interface.data),
+    .s_axis_qp_conn_interface_V_TVALID(s_axis_qp_conn_interface.valid),
+    .s_axis_qp_conn_interface_V_TREADY(s_axis_qp_conn_interface.ready),
+    .s_axis_qp_conn_interface_V_TDATA(s_axis_qp_conn_interface.data),
 
     //.local_ip_address_V(link_local_ipv6_address), // Use IPv6 addr
     .local_ip_address_V(local_ip_address), //Use IPv4 addr
@@ -140,6 +142,11 @@ rocev2_ip rocev2_inst(
     .regInvalidPsnDropCount_V(psn_drop_pkg_count_data),
     .regInvalidPsnDropCount_V_ap_vld(psn_drop_pkg_count_valid)
 );
+
+assign m_axis_rx_pcmeta.valid = 1'b0;
+assign m_axis_rx_pcmeta.data = 0;
+assign s_axis_tx_pcmeta.ready = 1'b1;
+
 end
 else begin
 assign s_axis_rx_data.ready = 1'b1;