https://stackoverflow.com/a/5432624

This is leveraging modern CPU designs:

• Branch misses are extremely costly, so no branches!
• CPUs have multiple logical units, so let's maximize parallelism
• Finally select the correct branch at the very end

We will need a strong microp architecture:

• Reads / writes must be linear offsets — MMU and registers must be siblings
• Writes must be u8 only — u16 needs to convert to 2x u8 microps
• Flag changes could be represented as 2x masks
• What about special logic?
  • jump / ret / call / rst
  • EI / DI
  • HALT / STOP