Context

At line 396 of embassy-stm32/src/ltdc.rs there is a block of code dedicated to setting the framebuffer pitch and line length:

// framebuffer pitch and line length
layer.cfblr().modify(|w| {
    w.set_cfbp(width * bytes_per_pixel);
    #[cfg(not(stm32u5))]
    w.set_cfbll(width * bytes_per_pixel + 7);
    #[cfg(stm32u5)]
    w.set_cfbll(width * bytes_per_pixel + 3);
});

Problem

This code does not work for the STM32F74xxx and STM32F75xxx. See section 18.7.23 of STM32F74xxx and STM32F75xxx reference manual revision 8. These processors should be part of the cfg statement for +3, not +7. As may be expected, with the code as it is, the whole screen gets sheared due to the misalignment.

Solution

I don't have a drop in solution at this time, otherwise this would be a PR. I have made a simple patch (I just switched the cfg statements) in a local copy of embassy to get by for now. This is my first time interacting with embassy, so I don't know exactly how to go about implementing a change like this (I have enough of an idea that I could probably do it, but not enough to be confident doing so). More important, however: I don't know if this is the only exception.

Is there a way to find out which processors need the +3 vs +7 that doesn't involve reading the datasheet for every processor with an LTDC?