Skip to content

Pull requests: efabless/caravel_mgmt_soc_litex

New pull request New
10 Open 75 Closed
10 Open 75 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

Add newfill cell to cvc pdk
#140 opened Dec 18, 2024 by M0stafaRady Loading…
2
Bug fixes: verilog/dv/tests-standalone/uart
#138 opened Sep 8, 2024 by edowson Loading…
Fix bug at user APIs access type
#137 opened Apr 15, 2024 by M0stafaRady Loading…
@algofoogle
1
Remove in correct double declaration of reg_debug_2 and reg_debug_1 defs.h
#134 opened Dec 4, 2023 by M0stafaRady Loading…
1
1
Added an initialization loop to the SPI flash emulation module
#133 opened Nov 15, 2023 by RTimothyEdwards Loading…
@RTimothyEdwards
2
Update Litex mgmt soc
#122 opened Feb 3, 2023 by tmichalak Loading…
5
Remove verilog/rtl/RAM128.v
#118 opened Nov 25, 2022 by antonblanchard Loading…
2
2nd attempt to push the simulation of caravan I/O and the simulation Verilog testbenches and simulation
#104 opened Oct 20, 2022 by RTimothyEdwards Loading…
@RTimothyEdwards
2
fix issue_34 flow Changes to Makefile and process flow
#35 opened Apr 4, 2022 by suppamax Loading…
1
verilog/dv/make: fix typo in comments flow Changes to Makefile and process flow
#28 opened Mar 17, 2022 by proppy Loading…
ProTip! Follow long discussions with comments:>50.