https://github.com/efabless/caravel_mgmt_soc_litex/blob/43d0ce33d331ee73d9dcebe197c6ce4da5909ecc/verilog/rtl/mgmt_core.v#L1774C31-L1774C31

This like appears to connect the SPI master controller Data Out Output Enable (active low) to the INVERTED signal of the SPI CS (active low) as a signal source. But surely with SPI, DO is only active when CS is active and they are both active low signals. So with this inversion in place it prevents the DO signal from making it to the external pin.

In my Arty-A7 port it was necessary to remove the tilde ~ character.

Maybe this is a left-over from GF180 which may have used Output Enable (active high) signals ? but sky130_fd_io_gpiov2 cells have Output Enable (active low) signals ?

Maybe as a workaround it is possible to reconfigure the gpio_control for the SPI CS PIN as necessary to achieve pull-down or pull-up, instead on expecting to be able to use the SPI master controller hardware device for this purpose, which I believe is the design intention.

EDIT: Sorry I mistyped the last paragraph and spoke in terms of CS and not DO concerning the use of gpio_control to workaround. But RTE has understood matters in his comment below. It is not the CS output that could be problematic, it is DO.