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SystemVerilog: string data type #1917

SystemVerilog: string data type

SystemVerilog: string data type #1917

Triggered via pull request January 3, 2025 13:06
Status Success
Total duration 1m 29s
Artifacts

syntax-checks.yaml

on: pull_request
check-clang-format
1m 20s
check-clang-format
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