/*

WARNING: Do NOT edit the input and output ports in this file in a text

editor if you plan to continue editing the block that represents it in

the Block Editor! File corruption is VERY likely to occur.

*/

/*

Copyright (C) 2023 Intel Corporation. All rights reserved.

Your use of Intel Corporation's design tools, logic functions

and other software and tools, and any partner logic

functions, and any output files from any of the foregoing

(including device programming or simulation files), and any

associated documentation or information are expressly subject

to the terms and conditions of the Intel Program License

Subscription Agreement, the Intel Quartus Prime License Agreement,

the Intel FPGA IP License Agreement, or other applicable license

agreement, including, without limitation, that your use is for

the sole purpose of programming logic devices manufactured by

Intel and sold by Intel or its authorized distributors. Please

refer to the applicable agreement for further details, at

https://fpgasoftware.intel.com/eula.

*/

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(text "fullstate" (rect 5 0 34 12)(font "Arial" ))

(text "inst" (rect 8 192 20 204)(font "Arial" ))

(port

(pt 0 32)

(input)

(text "buttonStart" (rect 0 0 42 12)(font "Arial" ))

(text "buttonStart" (rect 21 27 63 39)(font "Arial" ))

(line (pt 0 32)(pt 16 32)(line_width 1))

)

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(line (pt 0 48)(pt 16 48)(line_width 1))

)

(port

(pt 0 64)

(input)

(text "buttonReset" (rect 0 0 48 12)(font "Arial" ))

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(port

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(port

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(input)

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(port

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(output)

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(text "registerLoad" (rect 202 107 251 119)(font "Arial" ))

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(drawing

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)