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[nfc] Add testing of code blocks to CI
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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seldridge committed Feb 20, 2024
1 parent 9354d8c commit 78969a4
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16 changes: 16 additions & 0 deletions .github/workflows/continuous-integration-ci.yml
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Expand Up @@ -13,6 +13,7 @@ env:
pandoc-version: 3.1.11.1
pandoc-crossref-version: v0.3.17.0c
pandoc-install-dir: /opt/pandoc
tabby-cad-version: 2024-02-18

jobs:
markdown-to-pdf:
Expand Down Expand Up @@ -50,6 +51,21 @@ jobs:
sudo apt-get install graphviz latexmk texlive-latex-extra texlive-latex-recommended texlive-font-utils
- name: "Markdown -> [pandox] -> [TeXLive] -> PDF"
run: make
- name: Install Verilator (OSS CAD Suite)
shell: bash
run: |
VERSION=${{ env.tabby-cad-version }}
ARTIFACT=oss-cad-suite-linux-x64-$(echo $VERSION | tr -d '-')
wget -q -O - https://github.com/YosysHQ/oss-cad-suite-build/releases/download/${VERSION}/${ARTIFACT}.tgz | tar -zx
echo "$(pwd)/oss-cad-suite/bin" >> $GITHUB_PATH
- name: Install CIRCT
id: install-circt
uses: circt/install-circt@v1.1.1
with:
github-token: ${{ github.token }}
version-file: include/circt.json
- name: "Test code blocks"
run: make test
- name: "Upload Build Directory"
uses: actions/upload-artifact@v3
with:
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2 changes: 0 additions & 2 deletions abi.md
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Expand Up @@ -305,9 +305,7 @@ This layer, because it depends on `Layer1` being available, will automatically b
`include "layers_Foo_Layer1.sv"
bind Foo Foo_Layer1_Layer2 layer1_layer2(.bar_notNotA(Foo.bar.layer1_layer2.notNotA));
bind Bar Bar_Layer1_Layer2 layer1_layer2(.notA(Bar.layer1.notA));
// snippetbegin
`endif
// snippetend
```

The `` `ifdef ``{.verilog} guards enable any combination of the bind files to be included while still producing legal SystemVerilog.
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3 changes: 3 additions & 0 deletions include/circt.json
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@@ -0,0 +1,3 @@
{
"version": "firtool-1.66.0"
}
4 changes: 2 additions & 2 deletions spec.md
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Expand Up @@ -2838,6 +2838,7 @@ Example:

``` firrtl
FIRRTL version 4.0.0
;; snippetbegin
circuit Top:
module Top:
input x : {a: UInt<2>, flip b: UInt<2>}
Expand All @@ -2864,7 +2865,7 @@ circuit Top:
define xp = rwprobe(p)
connect p, x
connect y, p
;; snippetend
;; snippetend
```

## Limitations
Expand Down Expand Up @@ -4080,7 +4081,6 @@ The following string-encoded integer literals all have the value `-42`:
FIRRTL version 4.0.0
circuit Foo:
module Foo:
;; snippetbegin
node a = SInt<7>(
;; snippetbegin
-0b101010
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