- add probe IOs to FixedIOModuleSpec

- test fails with :<>= - make FixedIO___Modules work with Probe type IOs of Elem types - commented out code that doesn't work for Probe Type IOs of Aggregate types
chipsalliance · mwachs5 · May 30, 2024 · May 28, 2024 · May 28, 2024 · May 28, 2024
commit ba1e1f8f72ccdf4a83394030244b3dab9475db80
diff --git a/core/src/main/scala/chisel3/experimental/dataview/package.scala b/core/src/main/scala/chisel3/experimental/dataview/package.scala
@@ -154,7 +154,10 @@ package object dataview {
       case (aa: Aggregate, ba: Aggregate) =>
         if (!ba.typeEquivalent(aa)) {
           val fieldName = viewFieldLookup(ba)
-          throw InvalidViewException(s"field $fieldName specified as view of non-type-equivalent value $aa")
+          val result = ba.findFirstTypeMismatch(aa, strictTypes = true, strictWidths = true, strictProbeInfo = true)
+          throw InvalidViewException(
+            s"field $fieldName specified as view of non-type-equivalent value $aa due to $result"
+          )
         }
         getMatchedFields(aa, ba).foreach {
           case (aelt: Element, belt: Element) => onElt(aelt, belt)

diff --git a/core/src/main/scala/chisel3/internal/MonoConnect.scala b/core/src/main/scala/chisel3/internal/MonoConnect.scala
@@ -9,7 +9,7 @@ import chisel3.internal.containsProbe
 import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl.ir.{Connect, DefInvalid, ProbeDefine, PropAssign}
 import chisel3.internal.firrtl.Converter
-import chisel3.experimental.dataview.{isView, reify, reifyToAggregate}
+import chisel3.experimental.dataview.{isView, reify, reifySingleData, reifyToAggregate}
 import chisel3.properties.{Class, Property}
 import chisel3.reflect.DataMirror
 
@@ -439,11 +439,29 @@ private[chisel3] object MonoConnect {
   }
 
   def probeDefine(
-    sourceInfo: SourceInfo,
-    sink:       Data,
-    source:     Data,
-    context:    BaseModule
+    sourceInfo:  SourceInfo,
+    sinkProbe:   Data,
+    sourceProbe: Data,
+    context:     BaseModule
   ): Unit = {
+
+    // Reify sink and source if they're views
+    val sink = if (isView(sinkProbe)) {
+      reifySingleData(sinkProbe).getOrElse(
+        throwException(
+          s"If a DataView contains a Probe, it must resolve to one Data. $sinkProbe does not meet this criteria."
+        )
+      )
+    } else sinkProbe
+
+    val source = if (isView(sourceProbe)) {
+      reifySingleData(sourceProbe).getOrElse(
+        throwException(
+          s"If a DataView contains a Probe, it must resolve to one Data. $sourceProbe does not meet this criteria."
+        )
+      )
+    } else sourceProbe
+
     checkConnect.checkConnection(sourceInfo, sink, source, context)
     context match {
       case rm: RawModule => rm.addCommand(ProbeDefine(sourceInfo, sink.lref, source.ref))

diff --git a/src/test/scala/chiselTests/FixedIOModuleSpec.scala b/src/test/scala/chiselTests/FixedIOModuleSpec.scala
@@ -4,6 +4,10 @@ package chiselTests
 
 import chisel3._
 import circt.stage.ChiselStage
+import scala.collection.immutable.ListMap
+import chisel3.reflect.DataMirror.internal.chiselTypeClone
+import chisel3.experimental.SourceInfo
+import chisel3.probe.Probe
 
 class FixedIOModuleSpec extends ChiselFlatSpec with Utils with MatchesAndOmits {
 
@@ -88,4 +92,57 @@ class FixedIOModuleSpec extends ChiselFlatSpec with Utils with MatchesAndOmits {
       "input end : UInt<1>"
     )()
   }
+
+  "User defined FixedIORaw/ExtModules" should "be able to have Probes in their IOs" in {
+
+    class Agg extends Bundle {
+      val foo = Bool()
+      val bar = Bool()
+    }
+
+    class FixedIO extends Bundle {
+      val elem = Probe(Bool())
+      // val agg = Probe(new Agg())
+    }
+
+    class ExampleRaw extends FixedIORawModule[FixedIO](new FixedIO()) {
+
+      val elemWire = Wire(Bool())
+      elemWire := false.B
+      probe.define(io.elem, probe.ProbeValue(elemWire))
+
+      //val aggWire = Wire(new Agg())
+      //aggWire := DontCare
+      // probe.define(io.agg, probe.ProbeValue(aggWire))
+    }
+
+    class ExampleExt extends FixedIOExtModule[FixedIO](new FixedIO())
+
+    class Parent extends Module {
+      val childRaw = Module(new ExampleRaw())
+      val childExt = Module(new ExampleExt())
+      val outElemRaw = IO(Bool())
+      val probeElemWireRaw = Wire(Probe(Bool()))
+      outElemRaw := probe.read(probeElemWireRaw)
+      probeElemWireRaw :<>= childRaw.io.elem
+      val probeElemWireExt = Wire(Probe(Bool()))
+      val outElemExt = IO(Bool())
+      outElemExt := probe.read(probeElemWireExt)
+      probeElemWireExt :<>= childExt.io.elem
+
+      /* Doesn't work yet
+  val outAggRaw = IO(new Agg())
+  val probeAggWireRaw = Wire(Probe(new Agg()))
+  outAggRaw := probe.read(probeAggWireRaw)
+  probeAggWireRaw :<>= childRaw.io.agg
+  val probeAggWireExt = Wire(Probe(new Agg()))
+  val outAggExt = IO(new Agg())
+  outAggExt := probe.read(probeAggWireExt)
+  probeAggWireExt :<>= childExt.io.agg
+       */
+    }
+
+    print(circt.stage.ChiselStage.emitCHIRRTL(new Parent))
+
+  }
 }