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FixedIO__Modules with various kinds of probe ports #4105

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merged 13 commits into from
May 30, 2024
Merged

FixedIO__Modules with various kinds of probe ports #4105

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ba1e1f8
- add probe IOs to FixedIOModuleSpec
mwachs5 May 28, 2024
848107c
make the test actually test something and scalafmt
mwachs5 May 28, 2024
98fddcb
add more tests that also do not work
mwachs5 May 28, 2024
4f7472d
checkpoint which works for Probe-of-Aggregate
mwachs5 May 28, 2024
4c8eac6
getMatchedFields: don't recurse through probes.
dtzSiFive May 29, 2024
39ffaa7
more support for FixedIO
mwachs5 May 29, 2024
3cc327d
change names due to feedback
mwachs5 May 29, 2024
aa8c095
Merge remote-tracking branch 'origin/main' into probes-and-fixedio
mwachs5 May 29, 2024
941e684
cleanup and scalafmt
mwachs5 May 29, 2024
369a100
update scaladoc for FlatIO for probe types
mwachs5 May 29, 2024
5100de8
scalafmt
mwachs5 May 29, 2024
2d70341
add an import for scaladoc...?
mwachs5 May 29, 2024
f99df14
provide full path for scaladoc
mwachs5 May 29, 2024
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change names due to feedback
  • Loading branch information
@mwachs5
mwachs5 committed May 29, 2024
commit 3cc327d2c2685337681b2faeafbc7275ff24118d
20 changes: 10 additions & 10 deletions src/test/scala/chiselTests/FixedIOModuleSpec.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -98,19 +98,19 @@ class FixedIOModuleSpec extends ChiselFlatSpec with Utils with MatchesAndOmits {
val bar = Bool()
}

class Nested extends Bundle {
class AggWithProbes extends Bundle {
val foo = Probe(Bool())
val bar = Probe(Bool())
}

class FixedIO(probeAgg: Boolean, aggProbe: Boolean) extends Bundle {
class MixedBundle(probeAgg: Boolean, aggProbe: Boolean) extends Bundle {
val elem = Probe(Bool())
val agg = Option.when(probeAgg)(Probe(new Agg()))
val nested = Option.when(aggProbe)(new Nested())
val nested = Option.when(aggProbe)(new AggWithProbes())
}

class ExampleRaw(probeAgg: Boolean, aggProbe: Boolean)
extends FixedIORawModule[FixedIO](new FixedIO(probeAgg, aggProbe)) {
extends FixedIORawModule[MixedBundle](new MixedBundle(probeAgg, aggProbe)) {

val elemWire = Wire(Bool())
elemWire := false.B
Expand All @@ -123,7 +123,7 @@ class FixedIOModuleSpec extends ChiselFlatSpec with Utils with MatchesAndOmits {
}

if (aggProbe) {
val nestedWire = Wire(new Nested())
val nestedWire = Wire(new AggWithProbes())
val nestedFoo = WireInit(false.B)
val nestedBar = WireInit(false.B)
probe.define(nestedWire.foo, probe.ProbeValue(nestedFoo))
Expand All @@ -133,7 +133,7 @@ class FixedIOModuleSpec extends ChiselFlatSpec with Utils with MatchesAndOmits {
}

class ExampleExt(probeAgg: Boolean, aggProbe: Boolean)
extends FixedIOExtModule[FixedIO](new FixedIO(probeAgg, aggProbe))
extends FixedIOExtModule[MixedBundle](new MixedBundle(probeAgg, aggProbe))

class Parent(probeAgg: Boolean, aggProbe: Boolean) extends Module {
val childRaw = Module(new ExampleRaw(probeAgg, aggProbe))
Expand Down Expand Up @@ -162,14 +162,14 @@ class FixedIOModuleSpec extends ChiselFlatSpec with Utils with MatchesAndOmits {
}

if (aggProbe) {
val probeNestedWireRaw = Wire(new Nested())
val probeNestedWireRaw = Wire(new AggWithProbes())
val outNestedRawFoo = IO(Bool())
val outNestedRawBar = IO(Bool())
outNestedRawFoo := probe.read(probeNestedWireRaw.foo)
outNestedRawBar := probe.read(probeNestedWireRaw.bar)
probeNestedWireRaw :<>= childRaw.io.nested.get

val probeNestedWireExt = Wire(new Nested())
val probeNestedWireExt = Wire(new AggWithProbes())
val outNestedExtFoo = IO(Bool())
val outNestedExtBar = IO(Bool())
outNestedExtFoo := probe.read(probeNestedWireExt.foo)
Expand Down Expand Up @@ -237,11 +237,11 @@ class FixedIOModuleSpec extends ChiselFlatSpec with Utils with MatchesAndOmits {
}

"FixedIOExtModules" should "be able to have an Aggregate with Probes as its FixedIO" in {
class ProbeNestedExt extends FixedIOExtModule(new Nested())
class ProbeNestedExt extends FixedIOExtModule(new AggWithProbes())
class Parent extends RawModule {
val child = Module(new ProbeNestedExt)
val ioBar = IO(Output(new Bool()))
val wireNested = Wire(new Nested())
val wireNested = Wire(new AggWithProbes())
wireNested :<>= child.io
ioBar := probe.read(wireNested.bar)
}
Expand Down