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enhance(ci): add ci build matrix
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andelf committed Nov 1, 2024
1 parent 370cdaf commit eed2c09
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Showing 5 changed files with 94 additions and 8 deletions.
13 changes: 13 additions & 0 deletions .github/ci/build.sh
100644 → 100755
Original file line number Diff line number Diff line change
@@ -0,0 +1,13 @@
#!/bin/bash
## on pull_requrest

set -euo pipefail

# Build with all features
cargo build --features ${CHIP},embassy,rt,memory-x --no-default-features --target ${TARGET}

# Build without embassy
cargo build --features ${CHIP},rt --no-default-features --target ${TARGET}

# Build without embassy and rt
cargo build --features ${CHIP} --no-default-features --target ${TARGET}
37 changes: 37 additions & 0 deletions .github/workflows/build-examples.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,37 @@
name: Build Examples

on:
push:
branches: ["main"]
paths-ignore:
- "*.md"
pull_request:
branches: ["main"]
paths-ignore:
- "*.md"

env:
CARGO_TERM_COLOR: always

jobs:
build:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
- name: Use nightly Rust
run: |
rustup default nightly
rustup component add rust-src
rustup update
rustup target add riscv32imac-unknown-none-elf
rustup target add riscv32imafc-unknown-none-elf
rustup target add riscv32i-unknown-none-elf
- name: Fetch Deps
# if this is a pull request
if: github.event_name == 'pull_request'
run: |
mkdir -p ../ch32-data/build/
cd ../ch32-data/build/
git clone https://github.com/ch32-rs/ch32-metapac.git
- name: Build Only
run: ./.github/ci/build-examples.sh
41 changes: 39 additions & 2 deletions .github/workflows/build.yml
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
name: CI build
name: CI Build

on:
push:
Expand All @@ -15,6 +15,40 @@ env:

jobs:
build:
strategy:
matrix:
chip:
- ch32l103f8u6
- ch32v003f4u6
- ch32v103c8t6
- ch32v203f8u6
- ch32v208wbu6
- ch32v303vct6
- ch32v305fbp6
- ch32v307vct6
- ch32x035f7p6
- ch641
include:
- chip: ch32l103f8u6
target: riscv32imac-unknown-none-elf
- chip: ch32v003f4u6
target: riscv32i-unknown-none-elf
- chip: ch32v103c8t6
target: riscv32imac-unknown-none-elf
- chip: ch32v203f8u6
target: riscv32imac-unknown-none-elf
- chip: ch32v208wbu6
target: riscv32imac-unknown-none-elf
- chip: ch32v303vct6
target: riscv32imafc-unknown-none-elf
- chip: ch32v305fbp6
target: riscv32imafc-unknown-none-elf
- chip: ch32v307vct6
target: riscv32imafc-unknown-none-elf
- chip: ch32x035f7p6
target: riscv32imafc-unknown-none-elf
- chip: ch641
target: riscv32i-unknown-none-elf
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
Expand All @@ -34,4 +68,7 @@ jobs:
cd ../ch32-data/build/
git clone https://github.com/ch32-rs/ch32-metapac.git
- name: Build Only
run: ./.github/ci/build-examples.sh
run: ./.github/ci/build.sh
env:
CHIP: ${{ matrix.chip }}
TARGET: ${{ matrix.target }}
7 changes: 3 additions & 4 deletions Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,9 @@ embedded-hal-async = "1.0.0"

critical-section = { version = "1.2.0" }
defmt = { version = "0.3.8", optional = true }
embassy-sync = { version = "0.6.0", optional = true }
embassy-futures = { version = "0.1.1", optional = true }

embassy-sync = { version = "0.6.0" }
embassy-futures = { version = "0.1.1" }
embassy-time-driver = { version = "0.1.0", optional = true }
embassy-time = { version = "0.3.2", optional = true }
embassy-usb-driver = "0.1.0"
Expand Down Expand Up @@ -58,8 +59,6 @@ default = ["embassy", "rt"]
rt = ["dep:qingke-rt"]
highcode = ["qingke-rt/highcode"]
embassy = [
"dep:embassy-sync",
"dep:embassy-futures",
"dep:embassy-time-driver",
"dep:embassy-time",
]
Expand Down
4 changes: 2 additions & 2 deletions src/usbpd/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -161,7 +161,7 @@ impl<'d, T: Instance> UsbPdPhy<'d, T> {
// The detection voltage is 0.22V, sufficient to detect the default power(500mA/900mA)

T::port_cc_reg(self.cc1).modify(|w| w.set_cc_ce(vals::PortCcCe::V0_22));
embassy_time::Delay.delay_us(2);
crate::delay::Delay.delay_us(2);

if T::port_cc_reg(self.cc1).read().pa_cc_ai() {
// CC1 is connected
Expand All @@ -171,7 +171,7 @@ impl<'d, T: Instance> UsbPdPhy<'d, T> {
Ok(())
} else {
T::port_cc_reg(self.cc2).modify(|w| w.set_cc_ce(vals::PortCcCe::V0_22));
embassy_time::Delay.delay_us(2);
crate::delay::Delay.delay_us(2);

if T::port_cc_reg(self.cc2).read().pa_cc_ai() {
// CC2 is connected
Expand Down

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