This is a bad implementation of a subset of the RISCV32-I instruction set.

Encode simple.s into Calyx data format.

cargo run -- encode data/simple.s \
      --data ram:16:32:1 \
      --data reg_file:32:32 \
      --data dbg:1:32 \
      -o ../data/simple.json

Decode a calyx data file and read assembly instructions.

cargo run -- decode ../data/simple.json

Simulate the design with icarus verilog (was having some issues with Verilator)

cargo run --manifest-path=riscv-to-calyx/Cargo.toml -- \
      encode riscv-to-calyx/data/simple.s \
      --data ram:16:32:1 \
      --data reg_file:32:32 \
      --data dbg:1:32 \
      -o data/simple.json

fud e -q src/main.futil \
    -s verilog.data data/simple.json \
    --to dat --through icarus-verilog \
    -s verilog.cycle_limit 100000 | cargo run --manifest-path=riscv-to-calyx/Cargo.toml -- decode

Debug the design with a lovely vcd file

fud e src/main.futil \
    -s verilog.data data/simple.json \
    --to vcd --through icarus-verilog \
    -s calyx.flags " -p no-opt" \
    -s verilog.cycle_limit 1000 \
    -o dbg.vcd