Skip to content
View cairo-caplan's full-sized avatar
3 followers · 1 following
  • Grenoble, France

Highlights

  • Pro

Block or report cairo-caplan

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

  • vsdiat_pll Public

    BSD 3-Clause "New" or "Revised" License Updated Nov 25, 2021

  • core_ft60x_axi Public

    Forked from ultraembedded/core_ft60x_axi

    FTDI FT600 SuperSpeed USB3.0 to AXI bus master

    C++ GNU General Public License v3.0 Updated Jun 6, 2020

  • LimeSDR-USB_GW Public

    Forked from myriadrf/LimeSDR-USB_GW

    Altera Cyclone IV FPGA project for the USB 3.0 LimeSDR board

    Verilog 1 Apache License 2.0 Updated Mar 27, 2018

  • ri5cy Public

    Forked from embecosm/ri5cy

    The PULP RI5CY core modified for Verilator modeling and as a GDB server.

    SystemVerilog GNU General Public License v3.0 Updated Sep 21, 2017

  • fmc-adc-cbpf Public

    C 1 Updated Nov 24, 2016

  • fmc-adc-gui Public

    C++ Updated Nov 24, 2016

  • qt_root_example Public

    Example of a C++ project using Qt4/5 framework and CERN ROOT 5

    C++ Updated May 6, 2016

  • test-yosysjs Public

    Playing with yosysjs

    HTML 1 Updated Mar 24, 2016

  • HDL_Lib Public

    Set of HDL blocks and libraries

    VHDL 1 Updated Mar 2, 2016

  • CORDIC Public

    Serial CORDIC implemented in VHDL

    VHDL 1 Updated Jan 15, 2016

  • ComGPIB Public

    C++ Updated Jan 13, 2016

  • math-parser Public

    Automatically exported from code.google.com/p/math-parser

    C Updated Dec 31, 2015