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1. scr1 scr1 Public

   Forked from syntacore/scr1

   SCR1 is a high-quality open-source RISC-V MCU core in Verilog

   SystemVerilog

2. RISC-V-CPU RISC-V-CPU Public

   Forked from Evensgn/RISC-V-CPU

   RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

   Verilog

3. RISCV_CPU RISCV_CPU Public

   Forked from Michaelvll/RISCV_CPU

   A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

   C

4. riscv-simple-sv riscv-simple-sv Public

   Forked from tilk/riscv-simple-sv

   A simple RISC V core for teaching

   SystemVerilog

5. vscale vscale Public

   Forked from niosHD/vscale

   Verilog version of Z-scale

   Verilog

6. FPGAmp FPGAmp Public

   Forked from ultraembedded/FPGAmp

   FPGA Media Player

   C