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Merge branch 'ARCv3_HS5x_SMP' into ARC_Demo_common
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apower-syn committed Mar 6, 2024
2 parents c18025f + 3827e16 commit 4edb8e7
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125 changes: 125 additions & 0 deletions portable/ThirdParty/GCC/ARCv3_HS5x_SMP/arc/arc.h
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/*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2024 Synopsys, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
* 1 tab == 4 spaces!
*/

/**
* \file
* \ingroup ARC_HAL_CORE_COMM
* \brief header file including common core definitions
*/

/**
* \addtogroup ARC_HAL_CORE_COMM
* @{
*/

#ifndef _ARC_HAL_CORE_H_
#define _ARC_HAL_CORE_H_

#include "arc_feature_config.h"

#define AUX_BCR_TIMERS (0x75) /*!< build configuration for processor timers */
#define AUX_STATUS32 (0xa)
#define AUX_STATUS_BIT_AE (5) /*!< processor is in an exception */
#define AUX_STATUS_BIT_IE (31) /*!< interrupt enable */
#define AUX_STATUS_BIT_HALT (0) /*!< halt bit */
#define AUX_STATUS_BIT_SC (14) /*!< stack check bit */
#define AUX_STATUS_BIT_US (20) /*!< user sleep mode enable bit */
#define AUX_STATUS_MASK_IE (1 << AUX_STATUS_BIT_IE) /*!< mask of AUX_STATUS_BIT_IE */
#define AUX_STATUS_MASK_HALT (1 << AUX_STATUS_BIT_HALT) /*!< mask of AUX_STATUS_BIT_HALT */
#define AUX_STATUS_MASK_US (1 << AUX_STATUS_BIT_US) /*!< mask of AUX_STATUS_BIT_US */
#define STATUS32_RESET_VALUE (AUX_STATUS_MASK_US)
#define AUX_LP_START (0x2) /*!< loop start address (32-bit) */
#define AUX_LP_END (0x3) /*!< loop end address (32-bit) */
#define AUX_IDENTITY (0x4) /*!< core identity register (32-bit) */
#define AUX_IDENTITY_ARCVER_MASK (0x00FF) /*!< mask of core identity register ARCVER */
#define AUX_IDENTITY_ARCNUM_MASK (0xFF00) /*!< mask of core identity register ARCNUM */
#define AUX_KSTACK_TOP (0x264)
#define AUX_KSTACK_BASE (0x265)
#define AUX_TIMER0_CNT (0x21) /*!< timer 0 count value */
#define AUX_TIMER0_CTRL (0x22) /*!< timer 0 control value */
#define AUX_TIMER0_LIMIT (0x23) /*!< timer 0 limit value */
#define AUX_TIMER1_CNT (0x100) /*!< timer 1 count value */
#define AUX_TIMER1_CTRL (0x101) /*!< timer 1 control value */
#define AUX_TIMER1_LIMIT (0x102) /*!< timer 1 limit value */
#define AUX_RTC_CTRL (0x103) /*!< RTC control value */
#define AUX_RTC_LOW (0x104) /*!< RTC count low value */
#define AUX_RTC_HIGH (0x105) /*!< RTC count high value */
#define AUX_SECURE_TIMER0_CNT (0x106) /*!< secure timer 0 count value */
#define AUX_SECURE_TIMER0_CTRL (0x107) /*!< secure timer 0 control value */
#define AUX_SECURE_TIMER0_LIMIT (0x108) /*!< secure timer 0 limit value */
#define AUX_SECURE_TIMER1_CNT (0x109) /*!< secure timer 1 count value */
#define AUX_SECURE_TIMER1_CTRL (0x10a) /*!< secure timer 1 control value */
#define AUX_SECURE_TIMER1_LIMIT (0x10b) /*!< secure timer 1 limit value */
#define AUX_ERRET (0x400) /*!< exception return address */
#define AUX_ERBTA (0x401) /*!< BTA saved on exception entry */
#define AUX_ERSTATUS (0x402) /*!< STATUS32 saved on exception */
#define AUX_ECR (0x403) /*!< exception cause register */
#define AUX_IRQ_CTRL (0xe) /*!< interrupt context saving control register */
#define AUX_INT_VECT_BASE (0x25) /*!< interrupt vector base register */
#define AUX_IRQ_ACT (0x43) /*!< active interrupts register */
#define AUX_IRQ_CAUSE (0x40a) /*!< interrupt cause register */
#define AUX_IRQ_SELECT (0x40b) /*!< interrupt select register */
#define AUX_IRQ_PRIORITY (0x206) /*!< interrupt priority register */
#define AUX_IRQ_ENABLE (0x40c) /*!< interrupt enable register */
#define AUX_IRQ_TRIGGER (0x40d) /*!< interrupt trigger: level or pulse */
#define AUX_IRQ_STATUS (0x40f) /*!< interrupt status register */
#define AUX_IRQ_HINT (0x201) /*!< software interrupt trigger */

/* For SMP */
#define ARCONNECT_INTRPT_LINE (0x13) /*!< ARConnect Inter-core interrupt line, irq19 */

#define AUX_CONNECT_SYSTEM_BUILD (0xd0) /*!< ARConnect Build Configuration Register */
#define AUX_CONNECT_ICI_BUILD (0xe0) /*!< Inter-Core Interrupt Unit BCR */

#define ARCONNECT_CMD (0x600) /*!< ARConnect command register */
#define ARCONNECT_WDATA (0x601) /*!< ARConnect Write data register */
#define ARCONNECT_READBACK (0x602) /*!< ARConnect Read data register */
#define ARCONNECT_READBACK_64 (0x603) /*!< ARConnect Read 64-bit data register */

#define ARCONNECT_CMD_CHECK_CORE_ID (0x00) /*!< ARConnect command CMD_CHECK_CORE_ID */
#define ARCONNECT_CMD_INTRPT_GENERATE_IRQ (0x01) /*!< ARConnect command CMD_INTRPT_GENERATE_IRQ */
#define ARCONNECT_CMD_INTRPT_GENERATE_ACK (0x02) /*!< ARConnect command CMD_INTRPT_GENERATE_ACK */
#define ARCONNECT_CMD_INTRPT_READ_STATUS (0x03) /*!< ARConnect command CMD_INTRPT_READ_STATUS */
#define ARCONNECT_CMD_INTRPT_CHECK_SOURCE (0x04) /*!< ARConnect command CMD_INTRPT_CHECK_SOURCE */
/* End For SMP */

#ifndef __ASSEMBLY__

#include <stdint.h> /* C99 standard lib */
#include <limits.h> /* C99 standard lib */
#include <stddef.h> /* C99 standard lib */
#include <stdbool.h> /* C99 standard lib */

#define Inline static __inline__ /* inline function */

#define Asm __asm__ volatile /* inline asm (no optimization) */

#endif /* __ASSEMBLY__ */

#endif /* _ARC_HAL_CORE_H_ */

// /** @} */
264 changes: 264 additions & 0 deletions portable/ThirdParty/GCC/ARCv3_HS5x_SMP/arc/arc_asm_common.h
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/*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2024 Synopsys, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
* 1 tab == 4 spaces!
*/

/**
* \file
* \ingroup ARC_HAL_MISC
* \brief common macro definitions for assembly file
*/
/** @cond ARC_HAL_ASM_COMMON */

#ifndef _ARC_HAL_ASM_COMMON_H_
#define _ARC_HAL_ASM_COMMON_H_

#include "arc/arc.h"

#ifdef __ASSEMBLY__
/* the assembly macro definitions in ARC GNU and MWDT are
* different, so need different processing
*/
#if defined(__GNU__)
#define MACRO_ARG(x) \x
#define ASM_MACRO1(name, arg1) name arg1
#else
#define MACRO_ARG(x) x
#define ASM_MACRO1(name, arg1) name, arg1
#endif

/* Note on the LD/ST addr modes with addr reg wback
*
* LD.a same as LD.aw
*
* LD.a reg1, [reg2, x] => Pre Incr
* Eff Addr for load = [reg2 + x]
*
* LD.ab reg1, [reg2, x] => Post Incr
* Eff Addr for load = [reg2]
*/
.macro ASM_MACRO1(PUSHAX, aux)
lr r10, [MACRO_ARG(aux)]
PUSH r10
.endm

.macro ASM_MACRO1(POPAX, aux)
POP r10
sr r10, [MACRO_ARG(aux)]
.endm

/*--------------------------------------------------------------
* Helpers to save/restore callee-saved regs:
* used by several macros below
*-------------------------------------------------------------*/
.macro SAVE_CALLEE_REGS
PUSH r13
PUSH r14
PUSH r15
PUSH r16
PUSH r17
PUSH r18
PUSH r19
PUSH r20
PUSH r21
PUSH r22
PUSH r23
PUSH r24
PUSH r25
.endm

.macro RESTORE_CALLEE_REGS
POP r25
POP r24
POP r23
POP r22
POP r21
POP r20
POP r19
POP r18
POP r17
POP r16
POP r15
POP r14
POP r13
.endm

.macro SAVE_LP_REGS
PUSH r60
PUSHAX AUX_LP_START
PUSHAX AUX_LP_END
.endm

.macro RESTORE_LP_REGS
POPAX AUX_LP_END
POPAX AUX_LP_START
POP r10
/* must not use the LP_COUNT register(r60) as the destination of multi-cycle instruction */
mov r60, r10

.endm

/* macro to save r0 to r12 */
.macro SAVE_R0_TO_R12
PUSH r0
PUSH r1
PUSH r2
PUSH r3
PUSH r4
PUSH r5
PUSH r6
PUSH r7
PUSH r8
PUSH r9
PUSH r10
PUSH r11
PUSH r12
.endm

/* macro to restore r0 to r12 */
.macro RESTORE_R0_TO_R12
POP r12
POP r11
POP r10
POP r9
POP r8
POP r7
POP r6
POP r5
POP r4
POP r3
POP r2
POP r1
POP r0
.endm

/* macro to save all non-caller saved regs */
.macro SAVE_NONSCRATCH_REGS
/* caller saved regs are saved by caller function */
PUSH gp
PUSH fp
PUSH blink
SAVE_CALLEE_REGS
.endm

/* macro to restore all non-caller saved regs */
.macro RESTORE_NONSCRATCH_REGS
RESTORE_CALLEE_REGS
POP blink
POP fp
POP gp
.endm

/* normal interrupt prologue, pc, status and r0-r11 are saved by hardware */
.macro INTERRUPT_PROLOGUE
PUSH r12
PUSH gp
PUSH fp
PUSH ilink
PUSH r30

sub sp, sp, 4 /* skip bta */
.endm


/* normal interrupt epilogue, pc, status and r0-r11 are restored by hardware */
.macro INTERRUPT_EPILOGUE
add sp, sp, 4 /* skip bta */

POP r30
POP ilink
POP fp
POP gp
POP r12
.endm

/* exception prologue, create the same frame of interrupt manually */
.macro EXCEPTION_PROLOGUE
st.as r10, [sp, -8]
PUSHAX AUX_ERSTATUS
PUSHAX AUX_ERRET

SAVE_LP_REGS

PUSH blink

PUSH r11
sub sp, sp, 4 /* r10 is pushed before */
PUSH r9
PUSH r8
PUSH r7
PUSH r6
PUSH r5
PUSH r4
PUSH r3
PUSH r2
PUSH r1
PUSH r0

PUSH r12
PUSH gp
PUSH fp
PUSH ilink
PUSH r30

PUSHAX AUX_ERBTA
.endm

/* exception epilogue, restore the same frame of interrupt manually */
.macro EXCEPTION_EPILOGUE
POPAX AUX_ERBTA

POP r30
POP ilink
POP fp
POP gp
POP r12

POP r0
POP r1
POP r2
POP r3
POP r4
POP r5
POP r6
POP r7
POP r8
POP r9
add sp, sp, 4 /* r10 will be popped finally */
POP r11

POP blink

RESTORE_LP_REGS

POPAX AUX_ERRET
POPAX AUX_ERSTATUS

ld.as r10, [sp, -8]
.endm

#endif /* __ASSEMBLY__ */
#endif /* _ARC_HAL_ASM_COMMON_H */
/** @endcond */
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