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IODELAY

Pepijn de Vos edited this page Nov 19, 2024 · 5 revisions

IODELAY

The Gowin IODELAY primitive is a programmable delay unit that can be used for input or output logic in FPGA designs. It provides a total of 128 (0~127) delays, with single-step delay times of approximately 30ps for the GW1N series and 18ps for the GW2A series. The IODELAY module has multiple setting modes, including static mode, dynamic mode, and adaptive mode, allowing users to adjust the delay value as needed.

This device is not yet supported in Apicula

Ports

Port Size Direction
DF 1 output
DI 1 input
DLYSTEP 8 input
DO 1 output
SDTAP 1 input
VALUE 1 input

Parameters

Parameter Default Value
ADAPT_EN FALSE
C_STATIC_DLY 0 (0b00000000000000000000000000000000)
DYN_DLY_EN FALSE

Verilog Instantiation

IODELAY #(
    .ADAPT_EN(ADAPT_EN),
    .C_STATIC_DLY(C_STATIC_DLY),
    .DYN_DLY_EN(DYN_DLY_EN)
) iodelay_inst (
    .DF(DF),
    .DI(DI),
    .DLYSTEP(DLYSTEP),
    .DO(DO),
    .SDTAP(SDTAP),
    .VALUE(VALUE)
);

IODELAYA

This device is not yet supported in Apicula

Ports

Port Size Direction
DF 1 output
DI 1 input
DO 1 output
SDTAP 1 input
SETN 1 input
VALUE 1 input

Parameters

Parameter Default Value
C_STATIC_DLY 0 (0b00000000000000000000000000000000)

Verilog Instantiation

IODELAYA #(
    .C_STATIC_DLY(C_STATIC_DLY)
) iodelaya_inst (
    .DF(DF),
    .DI(DI),
    .DO(DO),
    .SDTAP(SDTAP),
    .SETN(SETN),
    .VALUE(VALUE)
);

IODELAYB

The IODELAYB module provides a total of 128 (0 to 127) delay, adding more delay adjustments compared to IODELAY. It can be used for I/O logic input, but not for I/O logic output.

This device is not yet supported in Apicula

Ports

Port Size Direction
DAADJ 2 input
DAO 1 output
DF 1 output
DI 1 input
DO 1 output
SDTAP 1 input
SETN 1 input
VALUE 1 input

Parameters

Parameter Default Value
C_STATIC_DLY 0 (0b00000000000000000000000000000000)
DA_SEL 0 (0b00)
DELAY_MUX 0 (0b00)

Verilog Instantiation

IODELAYB #(
    .C_STATIC_DLY(C_STATIC_DLY),
    .DA_SEL(DA_SEL),
    .DELAY_MUX(DELAY_MUX)
) iodelayb_inst (
    .DAADJ(DAADJ),
    .DAO(DAO),
    .DF(DF),
    .DI(DI),
    .DO(DO),
    .SDTAP(SDTAP),
    .SETN(SETN),
    .VALUE(VALUE)
);

IODELAYC

The IODELAYC module provides a total of 128 (0 to 127) delays, adding more delay adjustments compared to IODELAY. It can be used for I/O logic input, but not for I/O logic output.

This device is not yet supported in Apicula

Ports

Port Size Direction
DAADJ 2 input
DAO 1 output
DASEL 2 input
DF 1 output
DI 1 input
DO 1 output
SDTAP 1 input
SETN 1 input
VALUE 1 input

Parameters

Parameter Default Value
C_STATIC_DLY 0 (0b00000000000000000000000000000000)
DA_SEL 0 (0b00)
DYN_DA_SEL false

Verilog Instantiation

IODELAYC #(
    .C_STATIC_DLY(C_STATIC_DLY),
    .DA_SEL(DA_SEL),
    .DYN_DA_SEL(DYN_DA_SEL)
) iodelayc_inst (
    .DAADJ(DAADJ),
    .DAO(DAO),
    .DASEL(DASEL),
    .DF(DF),
    .DI(DI),
    .DO(DO),
    .SDTAP(SDTAP),
    .SETN(SETN),
    .VALUE(VALUE)
);
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