The Gowin DDRDLL primitive generates different phase delay steps based on a given input clock for clock phase shift. It can be driven by either GCLK or HCLK, and its output STEP signal controls DQS and DLLDLY modules. The STEP signal can also be routed to user logic. Additionally, the STEP signal is used to drive DQS and DLLDLY modules, and it has 8 bits of output delay step.

This device is not yet supported in Apicula

DDRDLL #(
    .CODESCAL(CODESCAL),
    .DIV_SEL(DIV_SEL),
    .DLL_FORCE(DLL_FORCE),
    .SCAL_EN(SCAL_EN)
) ddrdll_inst (
    .CLKIN(CLKIN),
    .LOCK(LOCK),
    .RESET(RESET),
    .STEP(STEP),
    .STOP(STOP),
    .UPDNCNTL(UPDNCNTL)
);