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Pepijn de Vos edited this page Nov 17, 2024 · 2 revisions

The Gowin DCS (Dynamic Clock Selector) primitive is used to dynamically switch between four clock inputs, GCLK0-GCLK3, via a CRU (Clock Router Unit). It has two clock switching modes: "Non-glitchless" and "Glitchless". In Non-glitchless mode, the output clock can glitch depending on the time of switching. In Glitchless mode, it is possible to avoid glitches by configuring the CLKSEL signal to switch the clock signal using DCS_MODE.

This device is supported in Apicula.

Ports

Port Size Direction
CLK0 1 input
CLK1 1 input
CLK2 1 input
CLK3 1 input
CLKOUT 1 output
CLKSEL 4 input
SELFORCE 1 input

Parameters

Parameter Default Value
DCS_MODE RISING

Verilog Instantiation

DCS #(
    .DCS_MODE(DCS_MODE)
) dcs_inst (
    .CLK0(CLK0),
    .CLK1(CLK1),
    .CLK2(CLK2),
    .CLK3(CLK3),
    .CLKOUT(CLKOUT),
    .CLKSEL(CLKSEL),
    .SELFORCE(SELFORCE)
);
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