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Add DHCEN primitive. #261

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merged 9 commits into from
Sep 12, 2024
Merged

Add DHCEN primitive. #261

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bea46f9
Add DHCEN primitive.
yrabbit Jul 20, 2024
90aaf55
DHCEN. Add example
yrabbit Jul 21, 2024
6889998
HCLK. Add interbank wires
yrabbit Jul 25, 2024
5af24fd
Merge with master
yrabbit Aug 13, 2024
efd2433
Add a DHCEN example.
yrabbit Aug 13, 2024
6da6ea2
DHCEN. Pass complete PIP not just wire
yrabbit Aug 17, 2024
ed0fc90
Merge branch 'master' into dhcen-ctl
yrabbit Sep 11, 2024
0964a8d
Merge branch 'dhcen-ctl' of github.com:yrabbit/apicula into dhcen-ctl
yrabbit Sep 11, 2024
af2975e
HCLK. Add delays
yrabbit Sep 11, 2024
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HCLK. Add delays 
Optimistic delays for now, pending future revision.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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@yrabbit
yrabbit committed Sep 11, 2024
commit af2975e67057763e3e0905e92614c9d13266a252
2 changes: 2 additions & 0 deletions apycula/chipdb.py
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Expand Up @@ -3576,6 +3576,8 @@ def fse_wire_delays(db):
db.wire_delay[clknames[i]] = "CENT_SPINE_PCLK"
for i in range(129, 153): # clock inputs (logic->clock)
db.wire_delay[clknames[i]] = "CENT_SPINE_PCLK"
for i in range(1000, 1010): # HCLK
db.wire_delay[clknames[i]] = "X0" # XXX

# assign pads with plls
# for now use static table and store the bel name although it is always PLL without a number
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2 changes: 1 addition & 1 deletion apycula/gowin_pack.py
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Expand Up @@ -2022,7 +2022,7 @@ def set_fuse():
if side == 'L':
col = 0
else:
col = db.col - 1
col = db.cols - 1
for row in range(db.rows):
set_fuse()

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