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Merge pull request #290 from YosysHQ/mul18
add missing examples to makefile
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,28 @@ | ||
`default_nettype none | ||
module top(input wire clk, | ||
input wire rst_i, | ||
input wire fclk_i, | ||
input wire data_i, | ||
output wire [7:0]q_o); | ||
|
||
assign q_o[2] = !rst_i; | ||
IDDR id( | ||
.D(data_i), | ||
.CLK(fclk_i), | ||
.Q0(q_o[0]), | ||
.Q1(q_o[1]) | ||
); | ||
defparam id.Q0_INIT=1'b0; | ||
defparam id.Q1_INIT=1'b0; | ||
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||
// dummy DFF | ||
assign q_o[4] = dummy_r; | ||
reg dummy_r; | ||
always @(posedge fclk_i) begin | ||
if (!rst_i) begin | ||
dummy_r <= 0; | ||
end else begin | ||
dummy_r <= !dummy_r; | ||
end | ||
end | ||
endmodule |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,25 @@ | ||
`default_nettype none | ||
module top(input wire clk, | ||
input wire rst_i, | ||
input wire fclk_i, | ||
input wire data_i, | ||
output wire [7:0]q_o); | ||
|
||
assign q_o[2] = !rst_i; | ||
IDDRC id( | ||
.D(data_i), | ||
.CLK(fclk_i), | ||
.CLEAR(!rst_i), | ||
.Q0(q_o[0]), | ||
.Q1(q_o[1]) | ||
); | ||
defparam id.Q0_INIT=1'b0; | ||
defparam id.Q1_INIT=1'b0; | ||
|
||
// dummy DFF | ||
assign q_o[4] = dummy_r; | ||
reg dummy_r; | ||
always @(posedge fclk_i) begin | ||
dummy_r <= !dummy_r; | ||
end | ||
endmodule |