alg/sha256.c: use _arm

Tarsnap · Feb 20, 2021 · 3050bca · 3050bca
1 parent 4b9a5e6
commit 3050bca
Showing 1 changed file with 24 additions and 1 deletion.
diff --git a/libcperciva/alg/sha256.c b/libcperciva/alg/sha256.c
@@ -4,6 +4,7 @@
 
 #include "cpusupport.h"
 #include "insecure_memzero.h"
+#include "sha256_arm.h"
 #include "sha256_shani.h"
 #include "sha256_sse2.h"
 #include "sysendian.h"
@@ -12,13 +13,15 @@
 #include "sha256.h"
 
 #if defined(CPUSUPPORT_X86_SHANI) && defined(CPUSUPPORT_X86_SSSE3) ||	\
-    defined(CPUSUPPORT_X86_SSE2)
+    defined(CPUSUPPORT_X86_SSE2) ||					\
+    defined(CPUSUPPORT_ARM_SHA256)
 #define HWACCEL
 
 enum {
 	HW_UNSET,
 	HW_X86_SHANI,
 	HW_X86_SSE2,
+	HW_ARM_SHA256,
 	HW_SOFTWARE
 };
 #endif
@@ -186,6 +189,21 @@ usehw(void)
 				    " self-test");
 			}
 		}
+#endif
+#if defined(CPUSUPPORT_ARM_SHA256)
+		/* If the CPU claims to be able to do it... */
+		if (cpusupport_arm_sha256()) {
+			/* ... test if it works... */
+			if (hwtest(initial_state, block, W, S,
+			    SHA256_Transform_arm)) {
+				warn0("Disabling ARM-SHA256 due to failed"
+				    " self-test");
+			} else
+				hwgood = HW_ARM_SHA256;
+
+			/* ... and bail whether or not we can use it. */
+			goto done;
+		}
 #endif
 	}
 
@@ -245,6 +263,11 @@ SHA256_Transform(uint32_t state[static restrict 8],
 	case HW_X86_SSE2:
 		SHA256_Transform_sse2(state, block, W, S);
 		return;
+#endif
+#if defined(CPUSUPPORT_ARM_SHA256)
+	case HW_ARM_SHA256:
+		SHA256_Transform_arm(state, block, W, S);
+		return;
 #endif
 	case HW_SOFTWARE:
 		break;